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c5e14e0478
This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276044 91177308-0d34-0410-b5e6-96231b3b80d8
633 lines
20 KiB
C++
633 lines
20 KiB
C++
//===-- RegisterScavenging.cpp - Machine register scavenging --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This file implements the machine register scavenger. It can provide
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/// information, such as unused registers, at any point in a machine basic
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/// block. It also provides a mechanism to make registers available by evicting
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/// them to spill slots.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "reg-scavenging"
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void RegScavenger::setRegUsed(unsigned Reg, LaneBitmask LaneMask) {
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for (MCRegUnitMaskIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) {
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LaneBitmask UnitMask = (*RUI).second;
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if (UnitMask == 0 || (LaneMask & UnitMask) != 0)
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RegUnitsAvailable.reset((*RUI).first);
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}
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}
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void RegScavenger::init(MachineBasicBlock &MBB) {
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MachineFunction &MF = *MBB.getParent();
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TII = MF.getSubtarget().getInstrInfo();
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TRI = MF.getSubtarget().getRegisterInfo();
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MRI = &MF.getRegInfo();
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assert((NumRegUnits == 0 || NumRegUnits == TRI->getNumRegUnits()) &&
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"Target changed?");
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// It is not possible to use the register scavenger after late optimization
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// passes that don't preserve accurate liveness information.
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assert(MRI->tracksLiveness() &&
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"Cannot use register scavenger with inaccurate liveness");
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// Self-initialize.
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if (!this->MBB) {
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NumRegUnits = TRI->getNumRegUnits();
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RegUnitsAvailable.resize(NumRegUnits);
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KillRegUnits.resize(NumRegUnits);
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DefRegUnits.resize(NumRegUnits);
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TmpRegUnits.resize(NumRegUnits);
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}
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this->MBB = &MBB;
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for (SmallVectorImpl<ScavengedInfo>::iterator I = Scavenged.begin(),
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IE = Scavenged.end(); I != IE; ++I) {
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I->Reg = 0;
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I->Restore = nullptr;
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}
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// All register units start out unused.
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RegUnitsAvailable.set();
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// Pristine CSRs are not available.
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BitVector PR = MF.getFrameInfo()->getPristineRegs(MF);
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for (int I = PR.find_first(); I>0; I = PR.find_next(I))
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setRegUsed(I);
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Tracking = false;
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}
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void RegScavenger::setLiveInsUsed(const MachineBasicBlock &MBB) {
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for (const auto &LI : MBB.liveins())
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setRegUsed(LI.PhysReg, LI.LaneMask);
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}
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void RegScavenger::enterBasicBlock(MachineBasicBlock &MBB) {
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init(MBB);
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setLiveInsUsed(MBB);
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}
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void RegScavenger::enterBasicBlockEnd(MachineBasicBlock &MBB) {
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init(MBB);
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// Merge live-ins of successors to get live-outs.
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for (const MachineBasicBlock *Succ : MBB.successors())
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setLiveInsUsed(*Succ);
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// Move internal iterator at the last instruction of the block.
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if (MBB.begin() != MBB.end()) {
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MBBI = std::prev(MBB.end());
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Tracking = true;
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}
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}
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void RegScavenger::addRegUnits(BitVector &BV, unsigned Reg) {
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for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
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BV.set(*RUI);
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}
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void RegScavenger::removeRegUnits(BitVector &BV, unsigned Reg) {
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for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
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BV.reset(*RUI);
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}
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void RegScavenger::determineKillsAndDefs() {
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assert(Tracking && "Must be tracking to determine kills and defs");
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MachineInstr &MI = *MBBI;
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assert(!MI.isDebugValue() && "Debug values have no kills or defs");
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// Find out which registers are early clobbered, killed, defined, and marked
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// def-dead in this instruction.
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KillRegUnits.reset();
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DefRegUnits.reset();
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for (const MachineOperand &MO : MI.operands()) {
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if (MO.isRegMask()) {
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TmpRegUnits.clear();
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for (unsigned RU = 0, RUEnd = TRI->getNumRegUnits(); RU != RUEnd; ++RU) {
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for (MCRegUnitRootIterator RURI(RU, TRI); RURI.isValid(); ++RURI) {
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if (MO.clobbersPhysReg(*RURI)) {
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TmpRegUnits.set(RU);
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break;
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}
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}
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}
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// Apply the mask.
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KillRegUnits |= TmpRegUnits;
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}
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!TargetRegisterInfo::isPhysicalRegister(Reg) || isReserved(Reg))
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continue;
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if (MO.isUse()) {
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// Ignore undef uses.
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if (MO.isUndef())
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continue;
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if (MO.isKill())
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addRegUnits(KillRegUnits, Reg);
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} else {
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assert(MO.isDef());
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if (MO.isDead())
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addRegUnits(KillRegUnits, Reg);
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else
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addRegUnits(DefRegUnits, Reg);
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}
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}
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}
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void RegScavenger::unprocess() {
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assert(Tracking && "Cannot unprocess because we're not tracking");
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MachineInstr &MI = *MBBI;
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if (!MI.isDebugValue()) {
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determineKillsAndDefs();
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// Commit the changes.
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setUsed(KillRegUnits);
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setUnused(DefRegUnits);
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}
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if (MBBI == MBB->begin()) {
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MBBI = MachineBasicBlock::iterator(nullptr);
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Tracking = false;
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} else
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--MBBI;
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}
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void RegScavenger::forward() {
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// Move ptr forward.
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if (!Tracking) {
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MBBI = MBB->begin();
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Tracking = true;
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} else {
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assert(MBBI != MBB->end() && "Already past the end of the basic block!");
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MBBI = std::next(MBBI);
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}
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assert(MBBI != MBB->end() && "Already at the end of the basic block!");
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MachineInstr &MI = *MBBI;
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for (SmallVectorImpl<ScavengedInfo>::iterator I = Scavenged.begin(),
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IE = Scavenged.end(); I != IE; ++I) {
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if (I->Restore != &MI)
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continue;
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I->Reg = 0;
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I->Restore = nullptr;
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}
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if (MI.isDebugValue())
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return;
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determineKillsAndDefs();
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// Verify uses and defs.
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#ifndef NDEBUG
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for (const MachineOperand &MO : MI.operands()) {
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!TargetRegisterInfo::isPhysicalRegister(Reg) || isReserved(Reg))
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continue;
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if (MO.isUse()) {
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if (MO.isUndef())
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continue;
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if (!isRegUsed(Reg)) {
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// Check if it's partial live: e.g.
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// D0 = insert_subreg D0<undef>, S0
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// ... D0
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// The problem is the insert_subreg could be eliminated. The use of
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// D0 is using a partially undef value. This is not *incorrect* since
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// S1 is can be freely clobbered.
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// Ideally we would like a way to model this, but leaving the
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// insert_subreg around causes both correctness and performance issues.
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bool SubUsed = false;
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for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
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if (isRegUsed(*SubRegs)) {
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SubUsed = true;
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break;
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}
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bool SuperUsed = false;
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for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
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if (isRegUsed(*SR)) {
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SuperUsed = true;
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break;
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}
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}
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if (!SubUsed && !SuperUsed) {
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MBB->getParent()->verify(nullptr, "In Register Scavenger");
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llvm_unreachable("Using an undefined register!");
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}
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(void)SubUsed;
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(void)SuperUsed;
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}
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} else {
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assert(MO.isDef());
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#if 0
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// FIXME: Enable this once we've figured out how to correctly transfer
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// implicit kills during codegen passes like the coalescer.
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assert((KillRegs.test(Reg) || isUnused(Reg) ||
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isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
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"Re-defining a live register!");
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#endif
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}
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}
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#endif // NDEBUG
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// Commit the changes.
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setUnused(KillRegUnits);
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setUsed(DefRegUnits);
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}
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void RegScavenger::backward() {
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assert(Tracking && "Must be tracking to determine kills and defs");
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const MachineInstr &MI = *MBBI;
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// Defined or clobbered registers are available now.
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for (const MachineOperand &MO : MI.operands()) {
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if (MO.isRegMask()) {
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for (unsigned RU = 0, RUEnd = TRI->getNumRegUnits(); RU != RUEnd;
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++RU) {
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for (MCRegUnitRootIterator RURI(RU, TRI); RURI.isValid(); ++RURI) {
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if (MO.clobbersPhysReg(*RURI)) {
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RegUnitsAvailable.set(RU);
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break;
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}
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}
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}
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} else if (MO.isReg() && MO.isDef()) {
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unsigned Reg = MO.getReg();
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if (!Reg || TargetRegisterInfo::isVirtualRegister(Reg) ||
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isReserved(Reg))
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continue;
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addRegUnits(RegUnitsAvailable, Reg);
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}
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}
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// Mark read registers as unavailable.
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for (const MachineOperand &MO : MI.uses()) {
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if (MO.isReg() && MO.readsReg()) {
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unsigned Reg = MO.getReg();
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if (!Reg || TargetRegisterInfo::isVirtualRegister(Reg) ||
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isReserved(Reg))
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continue;
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removeRegUnits(RegUnitsAvailable, Reg);
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}
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}
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// Expire scavenge spill frameindex uses.
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for (ScavengedInfo &I : Scavenged) {
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if (I.Restore == &MI) {
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I.Reg = 0;
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I.Restore = nullptr;
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}
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}
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if (MBBI == MBB->begin()) {
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MBBI = MachineBasicBlock::iterator(nullptr);
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Tracking = false;
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} else
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--MBBI;
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}
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bool RegScavenger::isRegUsed(unsigned Reg, bool includeReserved) const {
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if (includeReserved && isReserved(Reg))
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return true;
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for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
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if (!RegUnitsAvailable.test(*RUI))
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return true;
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return false;
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}
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unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
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for (unsigned Reg : *RC) {
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if (!isRegUsed(Reg)) {
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DEBUG(dbgs() << "Scavenger found unused reg: " << TRI->getName(Reg) <<
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"\n");
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return Reg;
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}
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}
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return 0;
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}
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BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) {
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BitVector Mask(TRI->getNumRegs());
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for (unsigned Reg : *RC)
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if (!isRegUsed(Reg))
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Mask.set(Reg);
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return Mask;
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}
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unsigned RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI,
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BitVector &Candidates,
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unsigned InstrLimit,
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MachineBasicBlock::iterator &UseMI) {
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int Survivor = Candidates.find_first();
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assert(Survivor > 0 && "No candidates for scavenging");
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MachineBasicBlock::iterator ME = MBB->getFirstTerminator();
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assert(StartMI != ME && "MI already at terminator");
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MachineBasicBlock::iterator RestorePointMI = StartMI;
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MachineBasicBlock::iterator MI = StartMI;
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bool inVirtLiveRange = false;
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for (++MI; InstrLimit > 0 && MI != ME; ++MI, --InstrLimit) {
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if (MI->isDebugValue()) {
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++InstrLimit; // Don't count debug instructions
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continue;
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}
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bool isVirtKillInsn = false;
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bool isVirtDefInsn = false;
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// Remove any candidates touched by instruction.
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for (const MachineOperand &MO : MI->operands()) {
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if (MO.isRegMask())
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Candidates.clearBitsNotInMask(MO.getRegMask());
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if (!MO.isReg() || MO.isUndef() || !MO.getReg())
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continue;
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if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
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if (MO.isDef())
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isVirtDefInsn = true;
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else if (MO.isKill())
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isVirtKillInsn = true;
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continue;
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}
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for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI)
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Candidates.reset(*AI);
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}
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// If we're not in a virtual reg's live range, this is a valid
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// restore point.
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if (!inVirtLiveRange) RestorePointMI = MI;
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// Update whether we're in the live range of a virtual register
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if (isVirtKillInsn) inVirtLiveRange = false;
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if (isVirtDefInsn) inVirtLiveRange = true;
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// Was our survivor untouched by this instruction?
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if (Candidates.test(Survivor))
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continue;
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// All candidates gone?
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if (Candidates.none())
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break;
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Survivor = Candidates.find_first();
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}
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// If we ran off the end, that's where we want to restore.
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if (MI == ME) RestorePointMI = ME;
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assert(RestorePointMI != StartMI &&
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"No available scavenger restore location!");
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// We ran out of candidates, so stop the search.
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UseMI = RestorePointMI;
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return Survivor;
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}
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static std::pair<unsigned, MachineBasicBlock::iterator>
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findSurvivorBackwards(const TargetRegisterInfo &TRI,
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MachineBasicBlock::iterator From, MachineBasicBlock::iterator To,
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BitVector &Available, BitVector &Candidates) {
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bool FoundTo = false;
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unsigned Survivor = 0;
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MachineBasicBlock::iterator Pos;
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MachineBasicBlock &MBB = *From->getParent();
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MachineBasicBlock::iterator I = From;
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unsigned InstrLimit = 25;
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unsigned InstrCountDown = InstrLimit;
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for (;;) {
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const MachineInstr &MI = *I;
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if (MI.isDebugValue())
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continue;
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// Remove any candidates touched by instruction.
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bool FoundVReg = false;
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for (const MachineOperand &MO : MI.operands()) {
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if (MO.isRegMask()) {
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Candidates.clearBitsNotInMask(MO.getRegMask());
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continue;
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}
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if (!MO.isReg() || MO.isUndef())
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continue;
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unsigned Reg = MO.getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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FoundVReg = true;
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} else if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
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Candidates.reset(*AI);
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}
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}
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if (I == To) {
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// If one of the available registers survived this long take it.
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Available &= Candidates;
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int Reg = Available.find_first();
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if (Reg != -1)
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return std::make_pair(Reg, MBB.end());
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// Otherwise we will continue up to InstrLimit instructions to fine
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// the register which is not defined/used for the longest time.
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FoundTo = true;
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Pos = To;
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}
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if (FoundTo) {
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if (Survivor == 0 || !Candidates.test(Survivor)) {
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int Reg = Candidates.find_first();
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if (Reg == -1)
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break;
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Survivor = Reg;
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}
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if (--InstrCountDown == 0 || I == MBB.begin())
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break;
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if (FoundVReg) {
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// We found a vreg, reset the InstrLimit counter.
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InstrCountDown = InstrLimit;
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Pos = I;
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}
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}
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--I;
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}
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return std::make_pair(Survivor, Pos);
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}
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static unsigned getFrameIndexOperandNum(MachineInstr &MI) {
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unsigned i = 0;
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while (!MI.getOperand(i).isFI()) {
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++i;
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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return i;
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}
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RegScavenger::ScavengedInfo &
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RegScavenger::spill(unsigned Reg, const TargetRegisterClass &RC, int SPAdj,
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MachineBasicBlock::iterator Before,
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MachineBasicBlock::iterator &UseMI) {
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// Find an available scavenging slot with size and alignment matching
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// the requirements of the class RC.
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const MachineFunction &MF = *Before->getParent()->getParent();
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const MachineFrameInfo &MFI = *MF.getFrameInfo();
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unsigned NeedSize = RC.getSize();
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unsigned NeedAlign = RC.getAlignment();
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unsigned SI = Scavenged.size(), Diff = UINT_MAX;
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int FIB = MFI.getObjectIndexBegin(), FIE = MFI.getObjectIndexEnd();
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for (unsigned I = 0; I < Scavenged.size(); ++I) {
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if (Scavenged[I].Reg != 0)
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continue;
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// Verify that this slot is valid for this register.
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int FI = Scavenged[I].FrameIndex;
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if (FI < FIB || FI >= FIE)
|
|
continue;
|
|
unsigned S = MFI.getObjectSize(FI);
|
|
unsigned A = MFI.getObjectAlignment(FI);
|
|
if (NeedSize > S || NeedAlign > A)
|
|
continue;
|
|
// Avoid wasting slots with large size and/or large alignment. Pick one
|
|
// that is the best fit for this register class (in street metric).
|
|
// Picking a larger slot than necessary could happen if a slot for a
|
|
// larger register is reserved before a slot for a smaller one. When
|
|
// trying to spill a smaller register, the large slot would be found
|
|
// first, thus making it impossible to spill the larger register later.
|
|
unsigned D = (S-NeedSize) + (A-NeedAlign);
|
|
if (D < Diff) {
|
|
SI = I;
|
|
Diff = D;
|
|
}
|
|
}
|
|
|
|
if (SI == Scavenged.size()) {
|
|
// We need to scavenge a register but have no spill slot, the target
|
|
// must know how to do it (if not, we'll assert below).
|
|
Scavenged.push_back(ScavengedInfo(FIE));
|
|
}
|
|
|
|
// Avoid infinite regress
|
|
Scavenged[SI].Reg = Reg;
|
|
|
|
// If the target knows how to save/restore the register, let it do so;
|
|
// otherwise, use the emergency stack spill slot.
|
|
if (!TRI->saveScavengerRegister(*MBB, Before, UseMI, &RC, Reg)) {
|
|
// Spill the scavenged register before \p Before.
|
|
int FI = Scavenged[SI].FrameIndex;
|
|
if (FI < FIB || FI >= FIE) {
|
|
std::string Msg = std::string("Error while trying to spill ") +
|
|
TRI->getName(Reg) + " from class " + TRI->getRegClassName(&RC) +
|
|
": Cannot scavenge register without an emergency spill slot!";
|
|
report_fatal_error(Msg.c_str());
|
|
}
|
|
TII->storeRegToStackSlot(*MBB, Before, Reg, true, Scavenged[SI].FrameIndex,
|
|
&RC, TRI);
|
|
MachineBasicBlock::iterator II = std::prev(Before);
|
|
|
|
unsigned FIOperandNum = getFrameIndexOperandNum(*II);
|
|
TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
|
|
|
|
// Restore the scavenged register before its use (or first terminator).
|
|
TII->loadRegFromStackSlot(*MBB, UseMI, Reg, Scavenged[SI].FrameIndex,
|
|
&RC, TRI);
|
|
II = std::prev(UseMI);
|
|
|
|
FIOperandNum = getFrameIndexOperandNum(*II);
|
|
TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
|
|
}
|
|
return Scavenged[SI];
|
|
}
|
|
|
|
unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
|
|
MachineBasicBlock::iterator I,
|
|
int SPAdj) {
|
|
MachineInstr &MI = *I;
|
|
const MachineFunction &MF = *MI.getParent()->getParent();
|
|
// Consider all allocatable registers in the register class initially
|
|
BitVector Candidates = TRI->getAllocatableSet(MF, RC);
|
|
|
|
// Exclude all the registers being used by the instruction.
|
|
for (const MachineOperand &MO : MI.operands()) {
|
|
if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) &&
|
|
!TargetRegisterInfo::isVirtualRegister(MO.getReg()))
|
|
Candidates.reset(MO.getReg());
|
|
}
|
|
|
|
// Try to find a register that's unused if there is one, as then we won't
|
|
// have to spill.
|
|
BitVector Available = getRegsAvailable(RC);
|
|
Available &= Candidates;
|
|
if (Available.any())
|
|
Candidates = Available;
|
|
|
|
// Find the register whose use is furthest away.
|
|
MachineBasicBlock::iterator UseMI;
|
|
unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
|
|
|
|
// If we found an unused register there is no reason to spill it.
|
|
if (!isRegUsed(SReg)) {
|
|
DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n");
|
|
return SReg;
|
|
}
|
|
|
|
ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI);
|
|
Scavenged.Restore = std::prev(UseMI);
|
|
|
|
DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) <<
|
|
"\n");
|
|
|
|
return SReg;
|
|
}
|
|
|
|
unsigned RegScavenger::scavengeRegisterBackwards(const TargetRegisterClass &RC,
|
|
MachineBasicBlock::iterator To,
|
|
bool RestoreAfter, int SPAdj) {
|
|
const MachineBasicBlock &MBB = *To->getParent();
|
|
const MachineFunction &MF = *MBB.getParent();
|
|
// Consider all allocatable registers in the register class initially
|
|
BitVector Candidates = TRI->getAllocatableSet(MF, &RC);
|
|
|
|
// Try to find a register that's unused if there is one, as then we won't
|
|
// have to spill.
|
|
BitVector Available = getRegsAvailable(&RC);
|
|
|
|
// Find the register whose use is furthest away.
|
|
MachineBasicBlock::iterator UseMI;
|
|
std::pair<unsigned, MachineBasicBlock::iterator> P =
|
|
findSurvivorBackwards(*TRI, MBBI, To, Available, Candidates);
|
|
unsigned Reg = P.first;
|
|
assert(Reg != 0 && "No register left to scavenge!");
|
|
// Found an available register?
|
|
if (!Available.test(Reg)) {
|
|
MachineBasicBlock::iterator ReloadBefore =
|
|
RestoreAfter ? std::next(MBBI) : MBBI;
|
|
DEBUG(dbgs() << "Reload before: " << *ReloadBefore << '\n');
|
|
ScavengedInfo &Scavenged = spill(Reg, RC, SPAdj, P.second, ReloadBefore);
|
|
Scavenged.Restore = std::prev(P.second);
|
|
addRegUnits(RegUnitsAvailable, Reg);
|
|
DEBUG(dbgs() << "Scavenged register with spill: " << PrintReg(Reg, TRI)
|
|
<< " until " << *P.second);
|
|
} else {
|
|
DEBUG(dbgs() << "Scavenged free register: " << PrintReg(Reg, TRI) << '\n');
|
|
}
|
|
return Reg;
|
|
}
|