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c783a5d937
Summary: The logic of dispatch remains the same, but now DispatchUnit is a Stage (DispatchStage). This change has the benefit of simplifying the backend runCycle() code. The same logic applies, but it belongs to different components now. This is just a start, eventually we will need to remove the call to the DispatchStage in Scheduler.cpp, but that will be a separate patch. This change is mostly a renaming and moving of existing logic. This change also encouraged me to remove the Subtarget (STI) member from the Backend class. That member was used to initialize the other members of Backend and to eventually call DispatchUnit::dispatch(). Now that we have Stages, we can eliminate this by instantiating the DispatchStage with everything it needs at the time of construction (e.g., Subtarget). That change allows us to call DispatchStage::execute(IR) as we expect to call execute() for all other stages. Once we add the Stage list (D46907) we can more cleanly call preExecute() on all of the stages, DispatchStage, will probably wrap cycleEvent() in that case. Made some formatting and minor cleanups to README.txt. Some of the text was re-flowed to stay within 80 cols. Reviewers: andreadb, courbet, RKSimon Reviewed By: andreadb, courbet Subscribers: mgorny, javed.absar, tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D46983 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332652 91177308-0d34-0410-b5e6-96231b3b80d8
96 lines
3.3 KiB
C++
96 lines
3.3 KiB
C++
//===---------------------- RetireControlUnit.cpp ---------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file implements methods declared by the RetireControlUnit interface.
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///
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//===----------------------------------------------------------------------===//
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#include "RetireControlUnit.h"
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#include "DispatchStage.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "llvm-mca"
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namespace mca {
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RetireControlUnit::RetireControlUnit(const llvm::MCSchedModel &SM,
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DispatchStage *DS)
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: NextAvailableSlotIdx(0), CurrentInstructionSlotIdx(0),
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AvailableSlots(SM.MicroOpBufferSize), MaxRetirePerCycle(0), Owner(DS) {
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// Check if the scheduling model provides extra information about the machine
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// processor. If so, then use that information to set the reorder buffer size
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// and the maximum number of instructions retired per cycle.
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if (SM.hasExtraProcessorInfo()) {
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const MCExtraProcessorInfo &EPI = SM.getExtraProcessorInfo();
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if (EPI.ReorderBufferSize)
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AvailableSlots = EPI.ReorderBufferSize;
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MaxRetirePerCycle = EPI.MaxRetirePerCycle;
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}
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assert(AvailableSlots && "Invalid reorder buffer size!");
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Queue.resize(AvailableSlots);
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}
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// Reserves a number of slots, and returns a new token.
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unsigned RetireControlUnit::reserveSlot(const InstRef &IR,
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unsigned NumMicroOps) {
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assert(isAvailable(NumMicroOps));
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unsigned NormalizedQuantity =
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std::min(NumMicroOps, static_cast<unsigned>(Queue.size()));
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// Zero latency instructions may have zero mOps. Artificially bump this
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// value to 1. Although zero latency instructions don't consume scheduler
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// resources, they still consume one slot in the retire queue.
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NormalizedQuantity = std::max(NormalizedQuantity, 1U);
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unsigned TokenID = NextAvailableSlotIdx;
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Queue[NextAvailableSlotIdx] = {IR, NormalizedQuantity, false};
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NextAvailableSlotIdx += NormalizedQuantity;
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NextAvailableSlotIdx %= Queue.size();
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AvailableSlots -= NormalizedQuantity;
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return TokenID;
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}
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void RetireControlUnit::cycleEvent() {
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if (isEmpty())
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return;
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unsigned NumRetired = 0;
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while (!isEmpty()) {
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if (MaxRetirePerCycle != 0 && NumRetired == MaxRetirePerCycle)
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break;
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RUToken &Current = Queue[CurrentInstructionSlotIdx];
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assert(Current.NumSlots && "Reserved zero slots?");
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assert(Current.IR.isValid() && "Invalid RUToken in the RCU queue.");
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if (!Current.Executed)
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break;
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Owner->notifyInstructionRetired(Current.IR);
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CurrentInstructionSlotIdx += Current.NumSlots;
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CurrentInstructionSlotIdx %= Queue.size();
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AvailableSlots += Current.NumSlots;
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NumRetired++;
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}
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}
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void RetireControlUnit::onInstructionExecuted(unsigned TokenID) {
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assert(Queue.size() > TokenID);
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assert(Queue[TokenID].Executed == false && Queue[TokenID].IR.isValid());
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Queue[TokenID].Executed = true;
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}
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#ifndef NDEBUG
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void RetireControlUnit::dump() const {
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dbgs() << "Retire Unit: { Total Slots=" << Queue.size()
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<< ", Available Slots=" << AvailableSlots << " }\n";
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}
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#endif
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} // namespace mca
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