RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2025-02-01 00:02:16 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity
llvm/test/CodeGen/ARM
History
Evan Cheng c7cf10c97e LR is in GPR, not tGPR even in Thumb1 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104518 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 18:00:18 +00:00
..
2006-11-10-CycleInDAG.ll
…
2007-01-19-InfiniteLoop.ll
…
2007-03-07-CombinerCrash.ll
…
2007-03-13-InstrSched.ll
…
2007-03-21-JoinIntervalsCrash.ll
…
2007-03-26-RegScavengerAssert.ll
…
2007-03-27-RegScavengerAssert.ll
…
2007-03-30-RegScavengerAssert.ll
…
2007-04-02-RegScavengerAssert.ll
…
2007-04-03-PEIBug.ll
…
2007-04-03-UndefinedSymbol.ll
…
2007-04-30-CombinerCrash.ll
…
2007-05-03-BadPostIndexedLd.ll
…
2007-05-07-jumptoentry.ll
…
2007-05-07-tailmerge-1.ll
…
2007-05-09-tailmerge-2.ll
…
2007-05-14-InlineAsmCstCrash.ll
…
2007-05-14-RegScavengerAssert.ll
…
2007-05-22-tailmerge-3.ll
…
2007-05-23-BadPreIndexedStore.ll
…
2007-05-31-RegScavengerInfiniteLoop.ll
…
2007-08-15-ReuseBug.ll
…
2008-02-04-LocalRegAllocBug.ll
…
2008-02-29-RegAllocLocal.ll
…
2008-03-05-SxtInRegBug.ll
…
2008-03-07-RegScavengerAssert.ll
…
2008-04-04-ScavengerAssert.ll
…
2008-04-10-ScavengerAssert.ll
…
2008-04-11-PHIofImpDef.ll
…
2008-05-19-LiveIntervalsBug.ll
…
2008-05-19-ScavengerAssert.ll
…
2008-07-17-Fdiv.ll
…
2008-07-24-CodeGenPrepCrash.ll
…
2008-08-07-AsmPrintBug.ll
…
2008-09-14-CoalescerBug.ll
…
2008-09-17-CoalescerBug.ll
…
2008-11-18-ScavengerAssert.ll
…
2009-02-16-SpillerBug.ll
…
2009-02-22-SoftenFloatVaArg.ll
…
2009-02-27-SpillerBug.ll
…
2009-03-07-SpillerBug.ll
…
2009-03-09-AddrModeBug.ll
…
2009-04-06-AsmModifier.ll
…
2009-04-08-AggregateAddr.ll
…
2009-04-08-FloatUndef.ll
…
2009-04-08-FREM.ll
…
2009-04-09-RegScavengerAsm.ll
…
2009-05-05-DAGCombineBug.ll
…
2009-05-07-RegAllocLocal.ll
…
2009-05-11-CodePlacementCrash.ll
…
2009-05-18-InlineAsmMem.ll
…
2009-06-02-ISelCrash.ll
…
2009-06-04-MissingLiveIn.ll
…
2009-06-12-RegScavengerAssert.ll
…
2009-06-15-RegScavengerAssert.ll
…
2009-06-19-RegScavengerAssert.ll
…
2009-06-22-CoalescerBug.ll
…
2009-06-30-RegScavengerAssert2.ll
…
2009-06-30-RegScavengerAssert3.ll
…
2009-06-30-RegScavengerAssert4.ll
…
2009-06-30-RegScavengerAssert5.ll
…
2009-06-30-RegScavengerAssert.ll
…
2009-07-01-CommuteBug.ll
…
2009-07-09-asm-p-constraint.ll
…
2009-07-18-RewriterBug.ll
…
2009-07-22-ScavengerAssert.ll
…
2009-07-22-SchedulerAssert.ll
…
2009-07-29-VFP3Registers.ll
…
2009-08-02-RegScavengerAssert-Neon.ll
…
2009-08-04-RegScavengerAssert-2.ll
…
2009-08-04-RegScavengerAssert.ll
…
2009-08-15-RegScavenger-EarlyClobber.ll
…
2009-08-15-RegScavengerAssert.ll
…
2009-08-21-PostRAKill2.ll
…
2009-08-21-PostRAKill3.ll
…
2009-08-21-PostRAKill4.ll
…
2009-08-21-PostRAKill.ll
…
2009-08-23-linkerprivate.ll
…
2009-08-26-ScalarToVector.ll
…
2009-08-27-ScalarToVector.ll
…
2009-08-29-ExtractEltf32.ll
…
2009-08-29-TooLongSplat.ll
…
2009-08-31-LSDA-Name.ll
…
2009-08-31-TwoRegShuffle.ll
…
2009-09-01-PostRAProlog.ll
…
2009-09-09-AllOnes.ll
…
2009-09-09-fpcmp-ole.ll
…
2009-09-10-postdec.ll
…
2009-09-13-InvalidSubreg.ll
…
2009-09-13-InvalidSuperReg.ll
…
2009-09-20-LiveIntervalsBug.ll
…
2009-09-21-LiveVariablesBug.ll
…
2009-09-22-LiveVariablesBug.ll
…
2009-09-23-LiveVariablesBug.ll
…
2009-09-24-spill-align.ll
…
2009-09-27-CoalescerBug.ll
…
2009-09-28-LdStOptiBug.ll
…
2009-10-02-NEONSubregsBug.ll
…
2009-10-21-InvalidFNeg.ll
…
2009-10-27-double-align.ll
…
2009-10-30.ll
…
2009-11-01-NeonMoves.ll
…
2009-11-02-NegativeLane.ll
Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements
2010-05-21 21:05:32 +00:00
2009-11-07-SubRegAsmPrinting.ll
…
2009-11-13-CoalescerCrash.ll
…
2009-11-13-ScavengerAssert2.ll
…
2009-11-13-ScavengerAssert.ll
…
2009-11-13-VRRewriterCrash.ll
…
2009-11-30-LiveVariablesBug.ll
…
2009-12-02-vtrn-undef.ll
…
2010-03-04-eabi-fp-spill.ll
…
2010-03-04-stm-undef-addr.ll
…
2010-03-18-ldm-rtrn.ll
…
2010-04-07-DbgValueOtherTargets.ll
…
2010-04-09-NeonSelect.ll
…
2010-04-13-v2f64SplitArg.ll
…
2010-04-14-SplitVector.ll
…
2010-04-15-ScavengerDebugValue.ll
…
2010-05-14-IllegalType.ll
…
2010-05-17-DAGCombineAssert.ll
FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op (build_vector), (build_vector)).
2010-05-18 00:03:40 +00:00
2010-05-17-FastAllocCrash.ll
…
2010-05-18-LocalAllocCrash.ll
Remember to update VirtRegLastUse when spilling without killing before a call.
2010-05-18 22:20:09 +00:00
2010-05-18-PostIndexBug.ll
Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649
2010-05-18 21:31:17 +00:00
2010-05-19-Shuffles.ll
Handle Neon v2f64 and v2i64 vector shuffles as register copies.
2010-05-20 18:39:53 +00:00
2010-05-20-NEONSpillCrash.ll
Teach VirtRegRewriter to handle spilling in instructions that have multiple
2010-05-21 16:36:13 +00:00
2010-05-21-BuildVector.ll
Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by
2010-05-22 00:23:12 +00:00
addrmode.ll
…
aliases.ll
…
align.ll
…
alloca.ll
…
argaddr.ll
…
arguments2.ll
…
arguments3.ll
…
arguments4.ll
…
arguments5.ll
…
arguments6.ll
…
arguments7.ll
…
arguments8.ll
…
arguments_f64_backfill.ll
…
arguments-nosplit-double.ll
…
arguments-nosplit-i64.ll
…
arguments.ll
…
arm-asm.ll
…
arm-frameaddr.ll
Implement @llvm.returnaddress. rdar://8015977.
2010-05-22 01:47:14 +00:00
arm-negative-stride.ll
…
arm-returnaddr.ll
LR is in GPR, not tGPR even in Thumb1 mode.
2010-05-24 18:00:18 +00:00
armv4.ll
…
bfc.ll
…
bfx.ll
…
bic.ll
…
bits.ll
…
bx_fold.ll
…
call_nolink.ll
…
call.ll
…
carry.ll
…
clz.ll
…
compare-call.ll
…
constants.ll
…
cse-libcalls.ll
…
ctors_dtors.ll
…
ctz.ll
…
dg.exp
…
div.ll
…
dyn-stackalloc.ll
…
extloadi1.ll
…
fabss.ll
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
2010-05-21 00:43:17 +00:00
fadds.ll
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
2010-05-21 00:43:17 +00:00
fcopysign.ll
…
fdivs.ll
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
2010-05-21 00:43:17 +00:00
fixunsdfdi.ll
…
fmacs.ll
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
2010-05-21 00:43:17 +00:00
fmdrr-fmrrd.ll
…
fmscs.ll
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
2010-05-21 00:43:17 +00:00
fmuls.ll
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
2010-05-21 00:43:17 +00:00
fnegs.ll
…
fnmacs.ll
…
fnmscs.ll
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
2010-05-21 00:43:17 +00:00
fnmul.ll
…
fnmuls.ll
…
formal.ll
…
fp16.ll
…
fp_convert.ll
…
fp.ll
…
fparith.ll
…
fpcmp_ueq.ll
…
fpcmp.ll
…
fpconsts.ll
…
fpconv.ll
…
fpmem.ll
…
fpow.ll
…
fpowi.ll
…
fptoint.ll
…
fsubs.ll
…
globals.ll
…
hardfloat_neon.ll
…
hello.ll
…
hidden-vis-2.ll
…
hidden-vis-3.ll
…
hidden-vis.ll
…
iabs.ll
…
ifcvt1.ll
…
ifcvt2.ll
…
ifcvt3.ll
…
ifcvt4.ll
…
ifcvt5.ll
…
ifcvt6.ll
…
ifcvt7.ll
…
ifcvt8.ll
…
ifcvt9.ll
…
illegal-vector-bitcast.ll
…
imm.ll
…
indirectbr.ll
…
inlineasm2.ll
…
inlineasm3.ll
…
inlineasm-imm-arm.ll
…
inlineasm.ll
…
insn-sched1.ll
…
ispositive.ll
…
large-stack.ll
…
ldm.ll
…
ldr_ext.ll
…
ldr_frame.ll
…
ldr_post.ll
…
ldr_pre.ll
…
ldr.ll
…
ldrd.ll
…
load.ll
…
long_shift.ll
…
long-setcc.ll
…
long.ll
…
lsr-code-insertion.ll
…
lsr-on-unrolled-loops.ll
When canonicalizing icmp operand order to put the loop invariant
2010-05-20 19:26:52 +00:00
lsr-scale-addr-mode.ll
…
mem.ll
…
memcpy-inline.ll
…
memfunc.ll
…
mls.ll
…
movt-movw-global.ll
…
movt.ll
…
mul_const.ll
…
mul.ll
…
mulhi.ll
…
mvn.ll
…
neon_arith1.ll
…
neon_ld1.ll
…
neon_ld2.ll
…
neon_minmax.ll
…
pack.ll
…
pr3502.ll
…
private.ll
…
reg_sequence.ll
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
2010-05-21 00:43:17 +00:00
remat.ll
…
ret0.ll
…
ret_arg1.ll
…
ret_arg2.ll
…
ret_arg3.ll
…
ret_arg4.ll
…
ret_arg5.ll
…
ret_f32_arg2.ll
…
ret_f32_arg5.ll
…
ret_f64_arg2.ll
…
ret_f64_arg_reg_split.ll
…
ret_f64_arg_split.ll
…
ret_f64_arg_stack.ll
…
ret_i64_arg2.ll
…
ret_i64_arg3.ll
…
ret_i64_arg_split.ll
…
ret_i128_arg2.ll
…
ret_void.ll
…
rev.ll
…
sbfx.ll
…
section.ll
…
select_xform.ll
…
select-imm.ll
…
select.ll
…
shifter_operand.ll
…
smul.ll
…
spill-q.ll
Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by
2010-05-22 00:23:12 +00:00
stack-frame.ll
…
stm.ll
…
str_post.ll
…
str_pre-2.ll
…
str_pre.ll
…
str_trunc.ll
…
sxt_rot.ll
…
t2-imm.ll
…
tail-opts.ll
…
thread_pointer.ll
…
tls1.ll
…
tls2.ll
…
tls3.ll
…
trap.ll
…
trunc_ldr.ll
…
truncstore-dag-combine.ll
…
tst_teq.ll
…
uint64tof64.ll
…
unaligned_load_store.ll
…
unord.ll
…
uxt_rot.ll
…
uxtb.ll
…
vaba.ll
…
vabd.ll
…
vabs.ll
…
vadd.ll
…
vargs_align.ll
…
vargs.ll
…
vbits.ll
…
vbsl.ll
…
vceq.ll
…
vcge.ll
…
vcgt.ll
Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction.
2010-05-19 01:08:17 +00:00
vcnt.ll
…
vcombine.ll
…
vcvt.ll
…
vdup.ll
…
vext.ll
…
vfcmp.ll
…
vfp.ll
…
vget_lane.ll
…
vhadd.ll
…
vhsub.ll
…
vicmp.ll
…
vld1.ll
…
vld2.ll
…
vld3.ll
…
vld4.ll
…
vldlane.ll
…
vminmax.ll
…
vmla.ll
…
vmls.ll
…
vmov.ll
…
vmul.ll
…
vneg.ll
…
vpadal.ll
…
vpadd.ll
…
vpminmax.ll
…
vqadd.ll
…
vqdmul.ll
…
vqshl.ll
…
vqshrn.ll
…
vqsub.ll
…
vrec.ll
…
vrev.ll
…
vshift.ll
…
vshiftins.ll
…
vshl.ll
…
vshll.ll
…
vshrn.ll
…
vsra.ll
…
vst1.ll
…
vst2.ll
…
vst3.ll
…
vst4.ll
…
vstlane.ll
…
vsub.ll
…
vtbl.ll
…
vtrn.ll
…
vuzp.ll
…
vzip.ll
…
weak2.ll
…
weak.ll
…