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d15cd2752f
the loop, and in both cases. In the first case, it is a VReg that is a constant so it may be actually converted to a constant. In the second case, it is already a constant, but then if it doesn't change its type (e.g. to become a register and have the value loaded from memory if it is too large to live in its instruction field), we must change the opcode BEFORE the 'continue', otherwise we miss the opportunity. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6602 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
InstrSched | ||
InstrSelection | ||
Mapping | ||
ModuloScheduling | ||
PostOpts | ||
PreOpts | ||
RegAlloc | ||
LiveVariables.cpp | ||
MachineCodeEmitter.cpp | ||
MachineCodeForInstruction.cpp | ||
MachineFunction.cpp | ||
MachineInstr.cpp | ||
MachineInstrAnnot.cpp | ||
Makefile | ||
PHIElimination.cpp | ||
PrologEpilogInserter.cpp | ||
RegAllocLocal.cpp | ||
RegAllocSimple.cpp |