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de55992d54
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214475 91177308-0d34-0410-b5e6-96231b3b80d8
584 lines
17 KiB
TableGen
584 lines
17 KiB
TableGen
//===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains instruction defs that are common to all hw codegen
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// targets.
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//
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//===----------------------------------------------------------------------===//
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class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
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field bit isRegisterLoad = 0;
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field bit isRegisterStore = 0;
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let Namespace = "AMDGPU";
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let OutOperandList = outs;
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let InOperandList = ins;
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let AsmString = asm;
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let Pattern = pattern;
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let Itinerary = NullALU;
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let TSFlags{63} = isRegisterLoad;
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let TSFlags{62} = isRegisterStore;
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}
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class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
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: AMDGPUInst<outs, ins, asm, pattern> {
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field bits<32> Inst = 0xffffffff;
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}
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def FP32Denormals : Predicate<"Subtarget.hasFP32Denormals()">;
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def FP64Denormals : Predicate<"Subtarget.hasFP64Denormals()">;
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def UnsafeFPMath : Predicate<"TM.Options.UnsafeFPMath">;
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def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
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def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
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let OperandType = "OPERAND_IMMEDIATE" in {
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def u32imm : Operand<i32> {
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let PrintMethod = "printU32ImmOperand";
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}
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def u16imm : Operand<i16> {
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let PrintMethod = "printU16ImmOperand";
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}
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def u8imm : Operand<i8> {
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let PrintMethod = "printU8ImmOperand";
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}
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} // End OperandType = "OPERAND_IMMEDIATE"
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//===--------------------------------------------------------------------===//
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// Custom Operands
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//===--------------------------------------------------------------------===//
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def brtarget : Operand<OtherVT>;
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//===----------------------------------------------------------------------===//
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// PatLeafs for floating-point comparisons
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//===----------------------------------------------------------------------===//
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def COND_OEQ : PatLeaf <
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(cond),
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[{return N->get() == ISD::SETOEQ || N->get() == ISD::SETEQ;}]
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>;
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def COND_OGT : PatLeaf <
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(cond),
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[{return N->get() == ISD::SETOGT || N->get() == ISD::SETGT;}]
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>;
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def COND_OGE : PatLeaf <
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(cond),
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[{return N->get() == ISD::SETOGE || N->get() == ISD::SETGE;}]
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>;
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def COND_OLT : PatLeaf <
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(cond),
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[{return N->get() == ISD::SETOLT || N->get() == ISD::SETLT;}]
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>;
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def COND_OLE : PatLeaf <
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(cond),
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[{return N->get() == ISD::SETOLE || N->get() == ISD::SETLE;}]
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>;
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def COND_UNE : PatLeaf <
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(cond),
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[{return N->get() == ISD::SETUNE || N->get() == ISD::SETNE;}]
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>;
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def COND_O : PatLeaf <(cond), [{return N->get() == ISD::SETO;}]>;
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def COND_UO : PatLeaf <(cond), [{return N->get() == ISD::SETUO;}]>;
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//===----------------------------------------------------------------------===//
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// PatLeafs for unsigned comparisons
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//===----------------------------------------------------------------------===//
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def COND_UGT : PatLeaf <(cond), [{return N->get() == ISD::SETUGT;}]>;
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def COND_UGE : PatLeaf <(cond), [{return N->get() == ISD::SETUGE;}]>;
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def COND_ULT : PatLeaf <(cond), [{return N->get() == ISD::SETULT;}]>;
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def COND_ULE : PatLeaf <(cond), [{return N->get() == ISD::SETULE;}]>;
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//===----------------------------------------------------------------------===//
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// PatLeafs for signed comparisons
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//===----------------------------------------------------------------------===//
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def COND_SGT : PatLeaf <(cond), [{return N->get() == ISD::SETGT;}]>;
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def COND_SGE : PatLeaf <(cond), [{return N->get() == ISD::SETGE;}]>;
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def COND_SLT : PatLeaf <(cond), [{return N->get() == ISD::SETLT;}]>;
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def COND_SLE : PatLeaf <(cond), [{return N->get() == ISD::SETLE;}]>;
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//===----------------------------------------------------------------------===//
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// PatLeafs for integer equality
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//===----------------------------------------------------------------------===//
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def COND_EQ : PatLeaf <
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(cond),
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[{return N->get() == ISD::SETEQ || N->get() == ISD::SETUEQ;}]
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>;
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def COND_NE : PatLeaf <
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(cond),
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[{return N->get() == ISD::SETNE || N->get() == ISD::SETUNE;}]
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>;
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def COND_NULL : PatLeaf <
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(cond),
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[{(void)N; return false;}]
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>;
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//===----------------------------------------------------------------------===//
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// Load/Store Pattern Fragments
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//===----------------------------------------------------------------------===//
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class PrivateMemOp <dag ops, dag frag> : PatFrag <ops, frag, [{
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return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
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}]>;
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class PrivateLoad <SDPatternOperator op> : PrivateMemOp <
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(ops node:$ptr), (op node:$ptr)
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>;
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class PrivateStore <SDPatternOperator op> : PrivateMemOp <
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(ops node:$value, node:$ptr), (op node:$value, node:$ptr)
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>;
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def extloadi8_private : PrivateLoad <extloadi8>;
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def sextloadi8_private : PrivateLoad <sextloadi8>;
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def extloadi16_private : PrivateLoad <extloadi16>;
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def sextloadi16_private : PrivateLoad <sextloadi16>;
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def load_private : PrivateLoad <load>;
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def truncstorei8_private : PrivateStore <truncstorei8>;
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def truncstorei16_private : PrivateStore <truncstorei16>;
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def store_private : PrivateStore <store>;
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def global_store : PatFrag<(ops node:$val, node:$ptr),
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(store node:$val, node:$ptr), [{
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return isGlobalStore(dyn_cast<StoreSDNode>(N));
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}]>;
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// Global address space loads
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def global_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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return isGlobalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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// Constant address space loads
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def constant_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
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}]>;
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def az_extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
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LoadSDNode *L = cast<LoadSDNode>(N);
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return L->getExtensionType() == ISD::ZEXTLOAD ||
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L->getExtensionType() == ISD::EXTLOAD;
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}]>;
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def az_extloadi8 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
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}]>;
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def az_extloadi8_global : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
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return isGlobalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def sextloadi8_global : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
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return isGlobalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def az_extloadi8_constant : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
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return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
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}]>;
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def sextloadi8_constant : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
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return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
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}]>;
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def az_extloadi8_local : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
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return isLocalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def sextloadi8_local : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
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return isLocalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def az_extloadi16 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
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}]>;
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def az_extloadi16_global : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
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return isGlobalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def sextloadi16_global : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
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return isGlobalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def az_extloadi16_constant : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
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return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
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}]>;
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def sextloadi16_constant : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
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return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
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}]>;
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def az_extloadi16_local : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
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return isLocalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def sextloadi16_local : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
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return isLocalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def az_extloadi32 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
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return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
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}]>;
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def az_extloadi32_global : PatFrag<(ops node:$ptr),
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(az_extloadi32 node:$ptr), [{
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return isGlobalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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def az_extloadi32_constant : PatFrag<(ops node:$ptr),
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(az_extloadi32 node:$ptr), [{
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return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
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}]>;
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def truncstorei8_global : PatFrag<(ops node:$val, node:$ptr),
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(truncstorei8 node:$val, node:$ptr), [{
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return isGlobalStore(dyn_cast<StoreSDNode>(N));
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}]>;
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def truncstorei16_global : PatFrag<(ops node:$val, node:$ptr),
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(truncstorei16 node:$val, node:$ptr), [{
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return isGlobalStore(dyn_cast<StoreSDNode>(N));
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}]>;
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def local_store : PatFrag<(ops node:$val, node:$ptr),
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(store node:$val, node:$ptr), [{
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return isLocalStore(dyn_cast<StoreSDNode>(N));
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}]>;
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def truncstorei8_local : PatFrag<(ops node:$val, node:$ptr),
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(truncstorei8 node:$val, node:$ptr), [{
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return isLocalStore(dyn_cast<StoreSDNode>(N));
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}]>;
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def truncstorei16_local : PatFrag<(ops node:$val, node:$ptr),
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(truncstorei16 node:$val, node:$ptr), [{
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return isLocalStore(dyn_cast<StoreSDNode>(N));
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}]>;
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def local_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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return isLocalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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class local_binary_atomic_op<SDNode atomic_op> :
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PatFrag<(ops node:$ptr, node:$value),
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(atomic_op node:$ptr, node:$value), [{
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return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
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}]>;
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def atomic_swap_local : local_binary_atomic_op<atomic_swap>;
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def atomic_load_add_local : local_binary_atomic_op<atomic_load_add>;
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def atomic_load_sub_local : local_binary_atomic_op<atomic_load_sub>;
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def atomic_load_and_local : local_binary_atomic_op<atomic_load_and>;
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def atomic_load_or_local : local_binary_atomic_op<atomic_load_or>;
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def atomic_load_xor_local : local_binary_atomic_op<atomic_load_xor>;
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def atomic_load_nand_local : local_binary_atomic_op<atomic_load_nand>;
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def atomic_load_min_local : local_binary_atomic_op<atomic_load_min>;
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def atomic_load_max_local : local_binary_atomic_op<atomic_load_max>;
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def atomic_load_umin_local : local_binary_atomic_op<atomic_load_umin>;
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def atomic_load_umax_local : local_binary_atomic_op<atomic_load_umax>;
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def mskor_global : PatFrag<(ops node:$val, node:$ptr),
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(AMDGPUstore_mskor node:$val, node:$ptr), [{
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return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
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}]>;
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def atomic_cmp_swap_32_local :
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PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
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(atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
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AtomicSDNode *AN = cast<AtomicSDNode>(N);
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return AN->getMemoryVT() == MVT::i32 &&
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AN->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
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}]>;
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def atomic_cmp_swap_64_local :
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PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
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(atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
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AtomicSDNode *AN = cast<AtomicSDNode>(N);
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return AN->getMemoryVT() == MVT::i64 &&
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AN->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
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}]>;
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//===----------------------------------------------------------------------===//
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// Misc Pattern Fragments
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//===----------------------------------------------------------------------===//
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def fmad : PatFrag <
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(ops node:$src0, node:$src1, node:$src2),
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(fadd (fmul node:$src0, node:$src1), node:$src2)
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>;
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class Constants {
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int TWO_PI = 0x40c90fdb;
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int PI = 0x40490fdb;
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int TWO_PI_INV = 0x3e22f983;
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int FP_UINT_MAX_PLUS_1 = 0x4f800000; // 1 << 32 in floating point encoding
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int FP32_NEG_ONE = 0xbf800000;
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int FP32_ONE = 0x3f800000;
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}
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def CONST : Constants;
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def FP_ZERO : PatLeaf <
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(fpimm),
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[{return N->getValueAPF().isZero();}]
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>;
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def FP_ONE : PatLeaf <
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(fpimm),
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[{return N->isExactlyValue(1.0);}]
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>;
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let isCodeGenOnly = 1, isPseudo = 1 in {
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let usesCustomInserter = 1 in {
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class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
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(outs rc:$dst),
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(ins rc:$src0),
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"CLAMP $dst, $src0",
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[(set f32:$dst, (AMDGPUclamp f32:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
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>;
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class FABS <RegisterClass rc> : AMDGPUShaderInst <
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(outs rc:$dst),
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(ins rc:$src0),
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"FABS $dst, $src0",
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[(set f32:$dst, (fabs f32:$src0))]
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>;
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class FNEG <RegisterClass rc> : AMDGPUShaderInst <
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(outs rc:$dst),
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(ins rc:$src0),
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"FNEG $dst, $src0",
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[(set f32:$dst, (fneg f32:$src0))]
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>;
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} // usesCustomInserter = 1
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multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass,
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ComplexPattern addrPat> {
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let UseNamedOperandTable = 1 in {
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def RegisterLoad : AMDGPUShaderInst <
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(outs dstClass:$dst),
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(ins addrClass:$addr, i32imm:$chan),
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"RegisterLoad $dst, $addr",
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[(set i32:$dst, (AMDGPUregister_load addrPat:$addr, (i32 timm:$chan)))]
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> {
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let isRegisterLoad = 1;
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}
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def RegisterStore : AMDGPUShaderInst <
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(outs),
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(ins dstClass:$val, addrClass:$addr, i32imm:$chan),
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"RegisterStore $val, $addr",
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[(AMDGPUregister_store i32:$val, addrPat:$addr, (i32 timm:$chan))]
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> {
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let isRegisterStore = 1;
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}
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}
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}
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} // End isCodeGenOnly = 1, isPseudo = 1
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/* Generic helper patterns for intrinsics */
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/* -------------------------------------- */
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class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul>
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: Pat <
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(fpow f32:$src0, f32:$src1),
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(exp_ieee (mul f32:$src1, (log_ieee f32:$src0)))
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>;
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/* Other helper patterns */
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/* --------------------- */
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/* Extract element pattern */
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class Extract_Element <ValueType sub_type, ValueType vec_type, int sub_idx,
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SubRegIndex sub_reg>
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: Pat<
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(sub_type (vector_extract vec_type:$src, sub_idx)),
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(EXTRACT_SUBREG $src, sub_reg)
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>;
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/* Insert element pattern */
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class Insert_Element <ValueType elem_type, ValueType vec_type,
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int sub_idx, SubRegIndex sub_reg>
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: Pat <
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(vector_insert vec_type:$vec, elem_type:$elem, sub_idx),
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(INSERT_SUBREG $vec, $elem, sub_reg)
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>;
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// XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
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// can handle COPY instructions.
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// bitconvert pattern
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class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
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(dt (bitconvert (st rc:$src0))),
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(dt rc:$src0)
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>;
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// XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
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// can handle COPY instructions.
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class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat <
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(vt (AMDGPUdwordaddr (vt rc:$addr))),
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(vt rc:$addr)
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>;
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// BFI_INT patterns
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multiclass BFIPatterns <Instruction BFI_INT, Instruction LoadImm32> {
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// Definition from ISA doc:
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// (y & x) | (z & ~x)
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def : Pat <
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(or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))),
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(BFI_INT $x, $y, $z)
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>;
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// SHA-256 Ch function
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// z ^ (x & (y ^ z))
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def : Pat <
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(xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))),
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(BFI_INT $x, $y, $z)
|
|
>;
|
|
|
|
def : Pat <
|
|
(fcopysign f32:$src0, f32:$src1),
|
|
(BFI_INT (LoadImm32 0x7fffffff), $src0, $src1)
|
|
>;
|
|
|
|
def : Pat <
|
|
(f64 (fcopysign f64:$src0, f64:$src1)),
|
|
(INSERT_SUBREG (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
|
|
(i32 (EXTRACT_SUBREG $src0, sub0)), sub0),
|
|
(BFI_INT (LoadImm32 0x7fffffff),
|
|
(i32 (EXTRACT_SUBREG $src0, sub1)),
|
|
(i32 (EXTRACT_SUBREG $src1, sub1))), sub1)
|
|
>;
|
|
}
|
|
|
|
// SHA-256 Ma patterns
|
|
|
|
// ((x & z) | (y & (x | z))) -> BFI_INT (XOR x, y), z, y
|
|
class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat <
|
|
(or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))),
|
|
(BFI_INT (XOR i32:$x, i32:$y), i32:$z, i32:$y)
|
|
>;
|
|
|
|
// Bitfield extract patterns
|
|
|
|
/*
|
|
|
|
XXX: The BFE pattern is not working correctly because the XForm is not being
|
|
applied.
|
|
|
|
def legalshift32 : ImmLeaf <i32, [{return Imm >=0 && Imm < 32;}]>;
|
|
def bfemask : PatLeaf <(imm), [{return isMask_32(N->getZExtValue());}],
|
|
SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(CountTrailingOnes_32(N->getZExtValue()), MVT::i32);}]>>;
|
|
|
|
class BFEPattern <Instruction BFE> : Pat <
|
|
(and (srl i32:$x, legalshift32:$y), bfemask:$z),
|
|
(BFE $x, $y, $z)
|
|
>;
|
|
|
|
*/
|
|
|
|
// rotr pattern
|
|
class ROTRPattern <Instruction BIT_ALIGN> : Pat <
|
|
(rotr i32:$src0, i32:$src1),
|
|
(BIT_ALIGN $src0, $src0, $src1)
|
|
>;
|
|
|
|
// 24-bit arithmetic patterns
|
|
def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>;
|
|
|
|
/*
|
|
class UMUL24Pattern <Instruction UMUL24> : Pat <
|
|
(mul U24:$x, U24:$y),
|
|
(UMUL24 $x, $y)
|
|
>;
|
|
*/
|
|
|
|
class IMad24Pat<Instruction Inst> : Pat <
|
|
(add (AMDGPUmul_i24 i32:$src0, i32:$src1), i32:$src2),
|
|
(Inst $src0, $src1, $src2)
|
|
>;
|
|
|
|
class UMad24Pat<Instruction Inst> : Pat <
|
|
(add (AMDGPUmul_u24 i32:$src0, i32:$src1), i32:$src2),
|
|
(Inst $src0, $src1, $src2)
|
|
>;
|
|
|
|
multiclass Expand24IBitOps<Instruction MulInst, Instruction AddInst> {
|
|
def _expand_imad24 : Pat <
|
|
(AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2),
|
|
(AddInst (MulInst $src0, $src1), $src2)
|
|
>;
|
|
|
|
def _expand_imul24 : Pat <
|
|
(AMDGPUmul_i24 i32:$src0, i32:$src1),
|
|
(MulInst $src0, $src1)
|
|
>;
|
|
}
|
|
|
|
multiclass Expand24UBitOps<Instruction MulInst, Instruction AddInst> {
|
|
def _expand_umad24 : Pat <
|
|
(AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2),
|
|
(AddInst (MulInst $src0, $src1), $src2)
|
|
>;
|
|
|
|
def _expand_umul24 : Pat <
|
|
(AMDGPUmul_u24 i32:$src0, i32:$src1),
|
|
(MulInst $src0, $src1)
|
|
>;
|
|
}
|
|
|
|
class RcpPat<Instruction RcpInst, ValueType vt> : Pat <
|
|
(fdiv FP_ONE, vt:$src),
|
|
(RcpInst $src)
|
|
>;
|
|
|
|
multiclass RsqPat<Instruction RsqInst, ValueType vt> {
|
|
def : Pat <
|
|
(fdiv FP_ONE, (fsqrt vt:$src)),
|
|
(RsqInst $src)
|
|
>;
|
|
|
|
def : Pat <
|
|
(AMDGPUrcp (fsqrt vt:$src)),
|
|
(RsqInst $src)
|
|
>;
|
|
}
|
|
|
|
include "R600Instructions.td"
|
|
include "R700Instructions.td"
|
|
include "EvergreenInstructions.td"
|
|
include "CaymanInstructions.td"
|
|
|
|
include "SIInstrInfo.td"
|
|
|