llvm/CodeGen at c8d65364223a04b179958a50a4bf0f89b21dd7d2 - llvm

RPCS3/llvm

mirror of https://github.com/RPCS3/llvm.git synced 2025-01-20 00:43:48 +00:00

History

Preston Gurd 1edadea42f For the current Atom processor, the fastest way to handle a call

indirect through a memory address is to load the memory address into
a register and then call indirect through the register.

This patch implements this improvement by modifying SelectionDAG to
force a function address which is a memory reference to be loaded
into a virtual register.

Patch by Sriram Murali.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178171 91177308-0d34-0410-b5e6-96231b3b80d8

2013-03-27 19:14:02 +00:00

AArch64

Update PEI's virtual-register-based scavenging to support multiple simultaneous mappings

2013-03-26 18:56:54 +00:00

ARM

Enabling the generation of dependency breakers for partial updates on Cortex-A15. Also fixing a small bug in getting the update clearence for VLD1LNd32.

2013-03-27 12:38:44 +00:00

CPP

test commit: remove blank line.

2013-03-14 05:43:59 +00:00

Generic

XFAIL some of the generic CodeGen tests for Hexagon.