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https://github.com/RPCS3/llvm.git
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31bf9d4967
Summary: Since the SPE4RC register class contains an identical set of registers and an identical spill size to the GPRC class its slightly confusing the tablegen emitter. It's preventing the GPRC_and_GPRC_NOR0 synthesized register class from inheriting VTs and AltOrders from GPRC or GPRC_NOR0. This is because SPE4C is found first in the super register class list when inheriting these properties and it doesn't set the VTs or AltOrders the same way as GPRC or GPRC_NOR0. This patch replaces all uses of GPE4RC with GPRC and allows GPRC and GPRC_NOR0 to contain f32. The test changes here are because the AltOrders are being inherited to GPRC_NOR0 now. Found while trying to determine if getCommonSubClass needs to take a VT argument. It was originally added to support fp128 on x86-64, I've changed some things about that so that it might be needed anymore. But a PowerPC test crashed without it and I think its due to this subclass issue. Reviewers: jhibbits, nemanjai, kbarton, hfinkel Subscribers: wuzish, nemanjai, mehdi_amini, hiraditya, kbarton, MaskRay, dexonsmith, jsji, shchenz, steven.zhang, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67513 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371779 91177308-0d34-0410-b5e6-96231b3b80d8
354 lines
13 KiB
C++
354 lines
13 KiB
C++
//===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/PPCMCTargetDesc.h"
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#include "TargetInfo/PowerPCTargetInfo.h"
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCFixedLenDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Endian.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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DEFINE_PPC_REGCLASSES;
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#define DEBUG_TYPE "ppc-disassembler"
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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namespace {
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class PPCDisassembler : public MCDisassembler {
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bool IsLittleEndian;
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public:
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PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
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bool IsLittleEndian)
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: MCDisassembler(STI, Ctx), IsLittleEndian(IsLittleEndian) {}
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DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &VStream,
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raw_ostream &CStream) const override;
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};
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} // end anonymous namespace
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static MCDisassembler *createPPCDisassembler(const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false);
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}
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static MCDisassembler *createPPCLEDisassembler(const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true);
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}
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extern "C" void LLVMInitializePowerPCDisassembler() {
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// Register the disassembler for each target.
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TargetRegistry::RegisterMCDisassembler(getThePPC32Target(),
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createPPCDisassembler);
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TargetRegistry::RegisterMCDisassembler(getThePPC64Target(),
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createPPCDisassembler);
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TargetRegistry::RegisterMCDisassembler(getThePPC64LETarget(),
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createPPCLEDisassembler);
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}
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static DecodeStatus DecodePCRel24BranchTarget(MCInst &Inst, unsigned Imm,
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uint64_t Addr,
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const void *Decoder) {
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int32_t Offset = SignExtend32<24>(Imm);
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Inst.addOperand(MCOperand::createImm(Offset));
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return MCDisassembler::Success;
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}
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// FIXME: These can be generated by TableGen from the existing register
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// encoding values!
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template <std::size_t N>
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static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
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const MCPhysReg (&Regs)[N]) {
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assert(RegNo < N && "Invalid register number");
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Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, CRRegs);
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}
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static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, CRBITRegs);
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}
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static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, FRegs);
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}
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static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, FRegs);
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}
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static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, VFRegs);
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}
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static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, VRegs);
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}
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static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, VSRegs);
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}
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static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, VSFRegs);
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}
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static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, VSSRegs);
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}
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static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, RRegs);
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}
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static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, RRegsNoR0);
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}
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static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, XRegs);
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}
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static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, XRegsNoX0);
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}
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#define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
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#define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
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static DecodeStatus DecodeQFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, QFRegs);
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}
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static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, SPERegs);
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}
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#define DecodeQSRCRegisterClass DecodeQFRCRegisterClass
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#define DecodeQBRCRegisterClass DecodeQFRCRegisterClass
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template<unsigned N>
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static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<N>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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template<unsigned N>
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static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<N>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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// Decode the memri field (imm, reg), which has the low 16-bits as the
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// displacement and the next 5 bits as the register #.
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uint64_t Base = Imm >> 16;
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uint64_t Disp = Imm & 0xFFFF;
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assert(Base < 32 && "Invalid base register");
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switch (Inst.getOpcode()) {
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default: break;
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case PPC::LBZU:
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case PPC::LHAU:
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case PPC::LHZU:
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case PPC::LWZU:
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case PPC::LFSU:
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case PPC::LFDU:
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// Add the tied output operand.
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Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
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break;
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case PPC::STBU:
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case PPC::STHU:
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case PPC::STWU:
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case PPC::STFSU:
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case PPC::STFDU:
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Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base]));
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break;
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}
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Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp)));
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Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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// Decode the memrix field (imm, reg), which has the low 14-bits as the
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// displacement and the next 5 bits as the register #.
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uint64_t Base = Imm >> 14;
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uint64_t Disp = Imm & 0x3FFF;
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assert(Base < 32 && "Invalid base register");
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if (Inst.getOpcode() == PPC::LDU)
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// Add the tied output operand.
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Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
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else if (Inst.getOpcode() == PPC::STDU)
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Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base]));
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Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2)));
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Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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// Decode the memrix16 field (imm, reg), which has the low 12-bits as the
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// displacement with 16-byte aligned, and the next 5 bits as the register #.
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uint64_t Base = Imm >> 12;
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uint64_t Disp = Imm & 0xFFF;
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assert(Base < 32 && "Invalid base register");
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Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4)));
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Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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// Decode the spe8disp field (imm, reg), which has the low 5-bits as the
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// displacement with 8-byte aligned, and the next 5 bits as the register #.
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uint64_t Base = Imm >> 5;
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uint64_t Disp = Imm & 0x1F;
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assert(Base < 32 && "Invalid base register");
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Inst.addOperand(MCOperand::createImm(Disp << 3));
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Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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// Decode the spe4disp field (imm, reg), which has the low 5-bits as the
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// displacement with 4-byte aligned, and the next 5 bits as the register #.
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uint64_t Base = Imm >> 5;
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uint64_t Disp = Imm & 0x1F;
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assert(Base < 32 && "Invalid base register");
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Inst.addOperand(MCOperand::createImm(Disp << 2));
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Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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// Decode the spe2disp field (imm, reg), which has the low 5-bits as the
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// displacement with 2-byte aligned, and the next 5 bits as the register #.
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uint64_t Base = Imm >> 5;
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uint64_t Disp = Imm & 0x1F;
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assert(Base < 32 && "Invalid base register");
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Inst.addOperand(MCOperand::createImm(Disp << 1));
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Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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// The cr bit encoding is 0x80 >> cr_reg_num.
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unsigned Zeros = countTrailingZeros(Imm);
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assert(Zeros < 8 && "Invalid CR bit value");
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Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros]));
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return MCDisassembler::Success;
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}
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#include "PPCGenDisassemblerTables.inc"
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DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address, raw_ostream &OS,
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raw_ostream &CS) const {
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// Get the four bytes of the instruction.
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Size = 4;
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if (Bytes.size() < 4) {
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Size = 0;
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return MCDisassembler::Fail;
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}
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// Read the instruction in the proper endianness.
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uint32_t Inst = IsLittleEndian ? support::endian::read32le(Bytes.data())
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: support::endian::read32be(Bytes.data());
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if (STI.getFeatureBits()[PPC::FeatureQPX]) {
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DecodeStatus result =
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decodeInstruction(DecoderTableQPX32, MI, Inst, Address, this, STI);
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if (result != MCDisassembler::Fail)
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return result;
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} else if (STI.getFeatureBits()[PPC::FeatureSPE]) {
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DecodeStatus result =
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decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI);
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if (result != MCDisassembler::Fail)
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return result;
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}
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return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);
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}
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