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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15851 91177308-0d34-0410-b5e6-96231b3b80d8
57 lines
1.8 KiB
C++
57 lines
1.8 KiB
C++
//===- PPC64InstrInfo.h - PowerPC64 Instruction Information -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC64 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef POWERPC64_INSTRUCTIONINFO_H
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#define POWERPC64_INSTRUCTIONINFO_H
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#include "PowerPCInstrInfo.h"
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#include "PPC64RegisterInfo.h"
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namespace llvm {
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class PPC64InstrInfo : public TargetInstrInfo {
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const PPC64RegisterInfo RI;
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public:
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PPC64InstrInfo();
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
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//
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// Return true if the instruction is a register to register move and
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// leave the source and dest operands in the passed parameters.
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//
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virtual bool isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg) const;
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static unsigned invertPPCBranchOpcode(unsigned Opcode) {
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switch (Opcode) {
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default: assert(0 && "Unknown PPC branch opcode!");
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case PPC::BEQ: return PPC::BNE;
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case PPC::BNE: return PPC::BEQ;
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case PPC::BLT: return PPC::BGE;
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case PPC::BGE: return PPC::BLT;
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case PPC::BGT: return PPC::BLE;
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case PPC::BLE: return PPC::BGT;
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}
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}
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};
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}
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#endif
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