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5bafff36c7
This is still a work in progress but most of the NEON instruction set is supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73919 91177308-0d34-0410-b5e6-96231b3b80d8
49 lines
1.6 KiB
LLVM
49 lines
1.6 KiB
LLVM
; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
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; RUN: grep {vclz\\.i8} %t | count 2
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; RUN: grep {vclz\\.i16} %t | count 2
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; RUN: grep {vclz\\.i32} %t | count 2
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define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = call <8 x i8> @llvm.arm.neon.vclz.v8i8(<8 x i8> %tmp1)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
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%tmp1 = load <4 x i16>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16> %tmp1)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vclz32(<2 x i32>* %A) nounwind {
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%tmp1 = load <2 x i32>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vclz.v2i32(<2 x i32> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind {
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%tmp1 = load <16 x i8>* %A
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%tmp2 = call <16 x i8> @llvm.arm.neon.vclz.v16i8(<16 x i8> %tmp1)
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind {
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%tmp1 = load <8 x i16>* %A
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%tmp2 = call <8 x i16> @llvm.arm.neon.vclz.v8i16(<8 x i16> %tmp1)
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind {
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vclz.v4i32(<4 x i32> %tmp1)
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ret <4 x i32> %tmp2
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}
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declare <8 x i8> @llvm.arm.neon.vclz.v8i8(<8 x i8>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vclz.v2i32(<2 x i32>) nounwind readnone
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declare <16 x i8> @llvm.arm.neon.vclz.v16i8(<16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vclz.v8i16(<8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vclz.v4i32(<4 x i32>) nounwind readnone
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