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ce63ffb52f
- Some clients which used DOUT have moved to DEBUG. We are deprecating the "magic" DOUT behavior which avoided calling printing functions when the statement was disabled. In addition to being unnecessary magic, it had the downside of leaving code in -Asserts builds, and of hiding potentially unnecessary computations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77019 91177308-0d34-0410-b5e6-96231b3b80d8
698 lines
22 KiB
C++
698 lines
22 KiB
C++
//===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Pass to verify generated machine code. The following is checked:
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//
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// Operand counts: All explicit operands must be present.
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//
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// Register classes: All physical and virtual register operands must be
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// compatible with the register class required by the instruction descriptor.
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//
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// Register live intervals: Registers must be defined only once, and must be
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// defined before use.
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//
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// The machine code verifier is enabled from LLVMTargetMachine.cpp with the
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// command-line option -verify-machineinstrs, or by defining the environment
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// variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
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// the verifier errors.
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//===----------------------------------------------------------------------===//
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#include "llvm/ADT/DenseSet.h"
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#include "llvm/ADT/SetOperations.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include <fstream>
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using namespace llvm;
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namespace {
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struct VISIBILITY_HIDDEN MachineVerifier : public MachineFunctionPass {
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static char ID; // Pass ID, replacement for typeid
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MachineVerifier(bool allowDoubleDefs = false) :
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MachineFunctionPass(&ID),
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allowVirtDoubleDefs(allowDoubleDefs),
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allowPhysDoubleDefs(allowDoubleDefs),
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OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
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{}
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void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesAll();
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}
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bool runOnMachineFunction(MachineFunction &MF);
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const bool allowVirtDoubleDefs;
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const bool allowPhysDoubleDefs;
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const char *const OutFileName;
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std::ostream *OS;
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const MachineFunction *MF;
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const TargetMachine *TM;
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const TargetRegisterInfo *TRI;
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const MachineRegisterInfo *MRI;
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unsigned foundErrors;
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typedef SmallVector<unsigned, 16> RegVector;
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typedef DenseSet<unsigned> RegSet;
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typedef DenseMap<unsigned, const MachineInstr*> RegMap;
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BitVector regsReserved;
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RegSet regsLive;
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RegVector regsDefined, regsImpDefined, regsDead, regsKilled;
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// Add Reg and any sub-registers to RV
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void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
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RV.push_back(Reg);
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if (TargetRegisterInfo::isPhysicalRegister(Reg))
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for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
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RV.push_back(*R);
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}
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// Does RS contain any super-registers of Reg?
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bool anySuperRegisters(const RegSet &RS, unsigned Reg) {
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for (const unsigned *R = TRI->getSuperRegisters(Reg); *R; R++)
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if (RS.count(*R))
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return true;
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return false;
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}
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struct BBInfo {
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// Is this MBB reachable from the MF entry point?
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bool reachable;
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// Vregs that must be live in because they are used without being
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// defined. Map value is the user.
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RegMap vregsLiveIn;
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// Vregs that must be dead in because they are defined without being
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// killed first. Map value is the defining instruction.
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RegMap vregsDeadIn;
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// Regs killed in MBB. They may be defined again, and will then be in both
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// regsKilled and regsLiveOut.
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RegSet regsKilled;
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// Regs defined in MBB and live out. Note that vregs passing through may
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// be live out without being mentioned here.
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RegSet regsLiveOut;
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// Vregs that pass through MBB untouched. This set is disjoint from
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// regsKilled and regsLiveOut.
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RegSet vregsPassed;
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BBInfo() : reachable(false) {}
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// Add register to vregsPassed if it belongs there. Return true if
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// anything changed.
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bool addPassed(unsigned Reg) {
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if (!TargetRegisterInfo::isVirtualRegister(Reg))
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return false;
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if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
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return false;
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return vregsPassed.insert(Reg).second;
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}
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// Same for a full set.
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bool addPassed(const RegSet &RS) {
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bool changed = false;
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for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
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if (addPassed(*I))
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changed = true;
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return changed;
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}
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// Live-out registers are either in regsLiveOut or vregsPassed.
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bool isLiveOut(unsigned Reg) const {
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return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
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}
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};
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// Extra register info per MBB.
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DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
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bool isReserved(unsigned Reg) {
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return Reg < regsReserved.size() && regsReserved[Reg];
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}
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void visitMachineFunctionBefore();
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void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
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void visitMachineInstrBefore(const MachineInstr *MI);
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void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
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void visitMachineInstrAfter(const MachineInstr *MI);
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void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
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void visitMachineFunctionAfter();
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void report(const char *msg, const MachineFunction *MF);
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void report(const char *msg, const MachineBasicBlock *MBB);
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void report(const char *msg, const MachineInstr *MI);
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void report(const char *msg, const MachineOperand *MO, unsigned MONum);
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void markReachable(const MachineBasicBlock *MBB);
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void calcMaxRegsPassed();
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void calcMinRegsPassed();
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void checkPHIOps(const MachineBasicBlock *MBB);
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};
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}
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char MachineVerifier::ID = 0;
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static RegisterPass<MachineVerifier>
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MachineVer("machineverifier", "Verify generated machine code");
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static const PassInfo *const MachineVerifyID = &MachineVer;
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FunctionPass *
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llvm::createMachineVerifierPass(bool allowPhysDoubleDefs)
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{
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return new MachineVerifier(allowPhysDoubleDefs);
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}
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bool
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MachineVerifier::runOnMachineFunction(MachineFunction &MF)
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{
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std::ofstream OutFile;
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if (OutFileName) {
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OutFile.open(OutFileName, std::ios::out | std::ios::app);
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OS = &OutFile;
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} else {
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OS = cerr.stream();
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}
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foundErrors = 0;
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this->MF = &MF;
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TM = &MF.getTarget();
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TRI = TM->getRegisterInfo();
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MRI = &MF.getRegInfo();
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visitMachineFunctionBefore();
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for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
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MFI!=MFE; ++MFI) {
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visitMachineBasicBlockBefore(MFI);
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for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
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MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
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visitMachineInstrBefore(MBBI);
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for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
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visitMachineOperand(&MBBI->getOperand(I), I);
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visitMachineInstrAfter(MBBI);
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}
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visitMachineBasicBlockAfter(MFI);
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}
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visitMachineFunctionAfter();
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if (OutFileName)
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OutFile.close();
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else if (foundErrors) {
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std::string msg;
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raw_string_ostream Msg(msg);
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Msg << "Found " << foundErrors << " machine code errors.";
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llvm_report_error(Msg.str());
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}
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return false; // no changes
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}
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void
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MachineVerifier::report(const char *msg, const MachineFunction *MF)
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{
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assert(MF);
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*OS << "\n";
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if (!foundErrors++)
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MF->print(OS);
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*OS << "*** Bad machine code: " << msg << " ***\n"
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<< "- function: " << MF->getFunction()->getNameStr() << "\n";
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}
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void
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MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB)
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{
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assert(MBB);
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report(msg, MBB->getParent());
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*OS << "- basic block: " << MBB->getBasicBlock()->getNameStr()
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<< " " << (void*)MBB
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<< " (#" << MBB->getNumber() << ")\n";
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}
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void
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MachineVerifier::report(const char *msg, const MachineInstr *MI)
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{
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assert(MI);
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report(msg, MI->getParent());
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*OS << "- instruction: ";
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MI->print(OS, TM);
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}
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void
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MachineVerifier::report(const char *msg,
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const MachineOperand *MO, unsigned MONum)
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{
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assert(MO);
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report(msg, MO->getParent());
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*OS << "- operand " << MONum << ": ";
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MO->print(*OS, TM);
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*OS << "\n";
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}
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void
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MachineVerifier::markReachable(const MachineBasicBlock *MBB)
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{
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BBInfo &MInfo = MBBInfoMap[MBB];
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if (!MInfo.reachable) {
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MInfo.reachable = true;
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for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
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SuE = MBB->succ_end(); SuI != SuE; ++SuI)
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markReachable(*SuI);
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}
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}
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void
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MachineVerifier::visitMachineFunctionBefore()
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{
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regsReserved = TRI->getReservedRegs(*MF);
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markReachable(&MF->front());
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}
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void
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MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB)
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{
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regsLive.clear();
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for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
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E = MBB->livein_end(); I != E; ++I) {
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if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
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report("MBB live-in list contains non-physical register", MBB);
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continue;
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}
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regsLive.insert(*I);
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for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
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regsLive.insert(*R);
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}
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regsKilled.clear();
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regsDefined.clear();
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regsImpDefined.clear();
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}
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void
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MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI)
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{
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const TargetInstrDesc &TI = MI->getDesc();
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if (MI->getNumExplicitOperands() < TI.getNumOperands()) {
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report("Too few operands", MI);
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*OS << TI.getNumOperands() << " operands expected, but "
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<< MI->getNumExplicitOperands() << " given.\n";
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}
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if (!TI.isVariadic()) {
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if (MI->getNumExplicitOperands() > TI.getNumOperands()) {
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report("Too many operands", MI);
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*OS << TI.getNumOperands() << " operands expected, but "
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<< MI->getNumExplicitOperands() << " given.\n";
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}
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}
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}
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void
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MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum)
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{
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const MachineInstr *MI = MO->getParent();
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const TargetInstrDesc &TI = MI->getDesc();
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// The first TI.NumDefs operands must be explicit register defines
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if (MONum < TI.getNumDefs()) {
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if (!MO->isReg())
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report("Explicit definition must be a register", MO, MONum);
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else if (!MO->isDef())
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report("Explicit definition marked as use", MO, MONum);
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else if (MO->isImplicit())
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report("Explicit definition marked as implicit", MO, MONum);
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}
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switch (MO->getType()) {
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case MachineOperand::MO_Register: {
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const unsigned Reg = MO->getReg();
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if (!Reg)
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return;
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// Check Live Variables.
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if (MO->isUse()) {
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if (MO->isKill()) {
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addRegWithSubRegs(regsKilled, Reg);
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// Tied operands on two-address instuctions MUST NOT have a <kill> flag.
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if (MI->isRegTiedToDefOperand(MONum))
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report("Illegal kill flag on two-address instruction operand",
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MO, MONum);
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} else {
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// TwoAddress instr modifying a reg is treated as kill+def.
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unsigned defIdx;
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if (MI->isRegTiedToDefOperand(MONum, &defIdx) &&
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MI->getOperand(defIdx).getReg() == Reg)
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addRegWithSubRegs(regsKilled, Reg);
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}
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// Explicit use of a dead register.
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if (!MO->isImplicit() && !regsLive.count(Reg)) {
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if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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// Reserved registers may be used even when 'dead'.
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if (!isReserved(Reg))
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report("Using an undefined physical register", MO, MONum);
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} else {
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BBInfo &MInfo = MBBInfoMap[MI->getParent()];
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// We don't know which virtual registers are live in, so only complain
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// if vreg was killed in this MBB. Otherwise keep track of vregs that
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// must be live in. PHI instructions are handled separately.
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if (MInfo.regsKilled.count(Reg))
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report("Using a killed virtual register", MO, MONum);
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else if (MI->getOpcode() != TargetInstrInfo::PHI)
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MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
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}
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}
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} else {
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// Register defined.
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// TODO: verify that earlyclobber ops are not used.
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if (MO->isImplicit())
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addRegWithSubRegs(regsImpDefined, Reg);
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else
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addRegWithSubRegs(regsDefined, Reg);
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if (MO->isDead())
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addRegWithSubRegs(regsDead, Reg);
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}
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// Check register classes.
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if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
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const TargetOperandInfo &TOI = TI.OpInfo[MONum];
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unsigned SubIdx = MO->getSubReg();
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if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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unsigned sr = Reg;
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if (SubIdx) {
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unsigned s = TRI->getSubReg(Reg, SubIdx);
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if (!s) {
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report("Invalid subregister index for physical register",
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MO, MONum);
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return;
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}
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sr = s;
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}
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if (TOI.RegClass) {
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const TargetRegisterClass *DRC = TRI->getRegClass(TOI.RegClass);
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if (!DRC->contains(sr)) {
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report("Illegal physical register for instruction", MO, MONum);
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*OS << TRI->getName(sr) << " is not a "
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<< DRC->getName() << " register.\n";
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}
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}
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} else {
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// Virtual register.
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const TargetRegisterClass *RC = MRI->getRegClass(Reg);
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if (SubIdx) {
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if (RC->subregclasses_begin()+SubIdx >= RC->subregclasses_end()) {
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report("Invalid subregister index for virtual register", MO, MONum);
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return;
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}
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RC = *(RC->subregclasses_begin()+SubIdx);
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}
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if (TOI.RegClass) {
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const TargetRegisterClass *DRC = TRI->getRegClass(TOI.RegClass);
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if (RC != DRC && !RC->hasSuperClass(DRC)) {
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report("Illegal virtual register for instruction", MO, MONum);
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*OS << "Expected a " << DRC->getName() << " register, but got a "
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<< RC->getName() << " register\n";
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}
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}
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}
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}
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break;
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}
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// Can PHI instrs refer to MBBs not in the CFG? X86 and ARM do.
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// case MachineOperand::MO_MachineBasicBlock:
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// if (MI->getOpcode() == TargetInstrInfo::PHI) {
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// if (!MO->getMBB()->isSuccessor(MI->getParent()))
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// report("PHI operand is not in the CFG", MO, MONum);
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// }
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// break;
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default:
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break;
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}
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}
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void
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MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI)
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{
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BBInfo &MInfo = MBBInfoMap[MI->getParent()];
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set_union(MInfo.regsKilled, regsKilled);
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set_subtract(regsLive, regsKilled);
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regsKilled.clear();
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for (RegVector::const_iterator I = regsDefined.begin(),
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E = regsDefined.end(); I != E; ++I) {
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if (regsLive.count(*I)) {
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if (TargetRegisterInfo::isPhysicalRegister(*I)) {
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// We allow double defines to physical registers with live
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// super-registers.
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if (!allowPhysDoubleDefs && !isReserved(*I) &&
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!anySuperRegisters(regsLive, *I)) {
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report("Redefining a live physical register", MI);
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*OS << "Register " << TRI->getName(*I)
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<< " was defined but already live.\n";
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}
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} else {
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if (!allowVirtDoubleDefs) {
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report("Redefining a live virtual register", MI);
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*OS << "Virtual register %reg" << *I
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<< " was defined but already live.\n";
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}
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}
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} else if (TargetRegisterInfo::isVirtualRegister(*I) &&
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!MInfo.regsKilled.count(*I)) {
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// Virtual register defined without being killed first must be dead on
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// entry.
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MInfo.vregsDeadIn.insert(std::make_pair(*I, MI));
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}
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}
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set_union(regsLive, regsDefined); regsDefined.clear();
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set_union(regsLive, regsImpDefined); regsImpDefined.clear();
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set_subtract(regsLive, regsDead); regsDead.clear();
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}
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void
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MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB)
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{
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MBBInfoMap[MBB].regsLiveOut = regsLive;
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regsLive.clear();
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}
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// Calculate the largest possible vregsPassed sets. These are the registers that
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// can pass through an MBB live, but may not be live every time. It is assumed
|
|
// that all vregsPassed sets are empty before the call.
|
|
void
|
|
MachineVerifier::calcMaxRegsPassed()
|
|
{
|
|
// First push live-out regs to successors' vregsPassed. Remember the MBBs that
|
|
// have any vregsPassed.
|
|
DenseSet<const MachineBasicBlock*> todo;
|
|
for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
|
|
MFI != MFE; ++MFI) {
|
|
const MachineBasicBlock &MBB(*MFI);
|
|
BBInfo &MInfo = MBBInfoMap[&MBB];
|
|
if (!MInfo.reachable)
|
|
continue;
|
|
for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
|
|
SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
|
|
BBInfo &SInfo = MBBInfoMap[*SuI];
|
|
if (SInfo.addPassed(MInfo.regsLiveOut))
|
|
todo.insert(*SuI);
|
|
}
|
|
}
|
|
|
|
// Iteratively push vregsPassed to successors. This will converge to the same
|
|
// final state regardless of DenseSet iteration order.
|
|
while (!todo.empty()) {
|
|
const MachineBasicBlock *MBB = *todo.begin();
|
|
todo.erase(MBB);
|
|
BBInfo &MInfo = MBBInfoMap[MBB];
|
|
for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
|
|
SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
|
|
if (*SuI == MBB)
|
|
continue;
|
|
BBInfo &SInfo = MBBInfoMap[*SuI];
|
|
if (SInfo.addPassed(MInfo.vregsPassed))
|
|
todo.insert(*SuI);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Calculate the minimum vregsPassed set. These are the registers that always
|
|
// pass live through an MBB. The calculation assumes that calcMaxRegsPassed has
|
|
// been called earlier.
|
|
void
|
|
MachineVerifier::calcMinRegsPassed()
|
|
{
|
|
DenseSet<const MachineBasicBlock*> todo;
|
|
for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
|
|
MFI != MFE; ++MFI)
|
|
todo.insert(MFI);
|
|
|
|
while (!todo.empty()) {
|
|
const MachineBasicBlock *MBB = *todo.begin();
|
|
todo.erase(MBB);
|
|
BBInfo &MInfo = MBBInfoMap[MBB];
|
|
|
|
// Remove entries from vRegsPassed that are not live out from all
|
|
// reachable predecessors.
|
|
RegSet dead;
|
|
for (RegSet::iterator I = MInfo.vregsPassed.begin(),
|
|
E = MInfo.vregsPassed.end(); I != E; ++I) {
|
|
for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
|
|
PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
|
|
BBInfo &PrInfo = MBBInfoMap[*PrI];
|
|
if (PrInfo.reachable && !PrInfo.isLiveOut(*I)) {
|
|
dead.insert(*I);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
// If any regs removed, we need to recheck successors.
|
|
if (!dead.empty()) {
|
|
set_subtract(MInfo.vregsPassed, dead);
|
|
todo.insert(MBB->succ_begin(), MBB->succ_end());
|
|
}
|
|
}
|
|
}
|
|
|
|
// Check PHI instructions at the beginning of MBB. It is assumed that
|
|
// calcMinRegsPassed has been run so BBInfo::isLiveOut is valid.
|
|
void
|
|
MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB)
|
|
{
|
|
for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
|
|
BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) {
|
|
DenseSet<const MachineBasicBlock*> seen;
|
|
|
|
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
|
|
unsigned Reg = BBI->getOperand(i).getReg();
|
|
const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
|
|
if (!Pre->isSuccessor(MBB))
|
|
continue;
|
|
seen.insert(Pre);
|
|
BBInfo &PrInfo = MBBInfoMap[Pre];
|
|
if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
|
|
report("PHI operand is not live-out from predecessor",
|
|
&BBI->getOperand(i), i);
|
|
}
|
|
|
|
// Did we see all predecessors?
|
|
for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
|
|
PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
|
|
if (!seen.count(*PrI)) {
|
|
report("Missing PHI operand", BBI);
|
|
*OS << "MBB #" << (*PrI)->getNumber()
|
|
<< " is a predecessor according to the CFG.\n";
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
MachineVerifier::visitMachineFunctionAfter()
|
|
{
|
|
calcMaxRegsPassed();
|
|
|
|
// With the maximal set of vregsPassed we can verify dead-in registers.
|
|
for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
|
|
MFI != MFE; ++MFI) {
|
|
BBInfo &MInfo = MBBInfoMap[MFI];
|
|
|
|
// Skip unreachable MBBs.
|
|
if (!MInfo.reachable)
|
|
continue;
|
|
|
|
for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
|
|
PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
|
|
BBInfo &PrInfo = MBBInfoMap[*PrI];
|
|
if (!PrInfo.reachable)
|
|
continue;
|
|
|
|
// Verify physical live-ins. EH landing pads have magic live-ins so we
|
|
// ignore them.
|
|
if (!MFI->isLandingPad()) {
|
|
for (MachineBasicBlock::const_livein_iterator I = MFI->livein_begin(),
|
|
E = MFI->livein_end(); I != E; ++I) {
|
|
if (TargetRegisterInfo::isPhysicalRegister(*I) &&
|
|
!isReserved (*I) && !PrInfo.isLiveOut(*I)) {
|
|
report("Live-in physical register is not live-out from predecessor",
|
|
MFI);
|
|
*OS << "Register " << TRI->getName(*I)
|
|
<< " is not live-out from MBB #" << (*PrI)->getNumber()
|
|
<< ".\n";
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
// Verify dead-in virtual registers.
|
|
if (!allowVirtDoubleDefs) {
|
|
for (RegMap::iterator I = MInfo.vregsDeadIn.begin(),
|
|
E = MInfo.vregsDeadIn.end(); I != E; ++I) {
|
|
// DeadIn register must be in neither regsLiveOut or vregsPassed of
|
|
// any predecessor.
|
|
if (PrInfo.isLiveOut(I->first)) {
|
|
report("Live-in virtual register redefined", I->second);
|
|
*OS << "Register %reg" << I->first
|
|
<< " was live-out from predecessor MBB #"
|
|
<< (*PrI)->getNumber() << ".\n";
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
calcMinRegsPassed();
|
|
|
|
// With the minimal set of vregsPassed we can verify live-in virtual
|
|
// registers, including PHI instructions.
|
|
for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
|
|
MFI != MFE; ++MFI) {
|
|
BBInfo &MInfo = MBBInfoMap[MFI];
|
|
|
|
// Skip unreachable MBBs.
|
|
if (!MInfo.reachable)
|
|
continue;
|
|
|
|
checkPHIOps(MFI);
|
|
|
|
for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
|
|
PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
|
|
BBInfo &PrInfo = MBBInfoMap[*PrI];
|
|
if (!PrInfo.reachable)
|
|
continue;
|
|
|
|
for (RegMap::iterator I = MInfo.vregsLiveIn.begin(),
|
|
E = MInfo.vregsLiveIn.end(); I != E; ++I) {
|
|
if (!PrInfo.isLiveOut(I->first)) {
|
|
report("Used virtual register is not live-in", I->second);
|
|
*OS << "Register %reg" << I->first
|
|
<< " is not live-out from predecessor MBB #"
|
|
<< (*PrI)->getNumber()
|
|
<< ".\n";
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|