Nicolai Haehnle 6435d005d6 AMDGPU: Prepare for explicit absolute relocations in code generation ...

Summary:
We will use absolute relocations for LDS symbols.

Change-Id: I9a32795ed0ea835e433a787129cfe3c57ee9a325

Reviewers: arsenm, rampitec

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D61492

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363517 91177308-0d34-0410-b5e6-96231b3b80d8

2019-06-16 17:43:37 +00:00

..

AArch64

adding more fmf propagation for selects plus updated tests

2019-06-15 04:53:51 +00:00

AMDGPU

AMDGPU: Be explicit about whether the high-word in SI_PC_ADD_REL_OFFSET is 0

2019-06-16 17:32:01 +00:00

ARC

[ARC] Add ARCOptAddrMode pass to generate postincrement loads/stores.

2019-03-20 20:06:21 +00:00

ARM

[MBP] Move a latch block with conditional exit and multi predecessors to top of loop

2019-06-14 23:08:59 +00:00

AVR

[AVR] Fix the 'avr-tiny.ll' and 'avr25.ll' subtarget feature tests

2019-06-12 08:31:07 +00:00

BPF

[BPF] generate R_BPF_NONE relocation for BTF DataSec variables

2019-05-26 21:26:06 +00:00

Generic

Improve reduction intrinsics by overloading result value.

2019-06-13 09:37:38 +00:00

Hexagon

[MBP] Move a latch block with conditional exit and multi predecessors to top of loop

2019-06-14 23:08:59 +00:00

Inputs

…

Lanai

[DAGCombine][X86][AArch64][MIPS][LANAI] (C - x) - y -> C - (x + y) fold (PR41952)

2019-06-04 11:06:21 +00:00

Mips

[FastISel] Skip creating unnecessary vregs for arguments

2019-06-10 16:53:37 +00:00

MIR

AMDGPU: Prepare for explicit absolute relocations in code generation

2019-06-16 17:43:37 +00:00

MSP430

[AsmPrinter] refactor to support %c w/ GlobalAddress'

2019-04-26 18:45:04 +00:00

NVPTX

SelectionDAG: accommodate atomic floating stores.

2019-05-10 11:23:04 +00:00

PowerPC

[PowerPC] Set the innermost hot loop to align 32 bytes

2019-06-15 15:10:24 +00:00

RISCV

[RISCV] Regenerate remat.ll and atomic-rmw.ll after D43256

2019-06-15 07:49:14 +00:00

SPARC

[DAGCombiner][X86][AArch64][SPARC][SystemZ] y - (x + C) -> (y - x) - C fold. Try 3

2019-05-30 20:37:18 +00:00

SystemZ

[MBP] Move a latch block with conditional exit and multi predecessors to top of loop

2019-06-14 23:08:59 +00:00

Thumb

[MBP] Move a latch block with conditional exit and multi predecessors to top of loop

2019-06-14 23:08:59 +00:00

Thumb2

[Codegen] Merge tail blocks with no successors after block placement

2019-06-13 18:11:32 +00:00

WebAssembly

[WebAssembly] Limit PIC support to the Emscripten target

2019-06-05 20:01:01 +00:00

WinCFGuard

[COFF] Emit @feat.00 on 64-bit and set the CFG bit when emitting guardcf tables

2018-09-19 09:58:30 +00:00

WinEH

[Codegen] Merge tail blocks with no successors after block placement

2019-06-13 18:11:32 +00:00

X86

[CodeGenPrepare][x86] shift both sides of a vector select when profitable

2019-06-16 15:29:03 +00:00

XCore

Revert "[NFC][CodeGen] Add unary FNeg tests to some X86/ and XCore/ tests."

2019-06-13 19:24:51 +00:00