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![Simon Pilgrim](/assets/img/avatar_default.png)
Similar to what we do for vXi8 ASHR(X, 7), use SSE42's PCMPGTQ to splat the sign instead of using the PSRAD+PSHUFD. Avoiding bitcasts this improves combines that utilize computeNumSignBits, permits memory folding and reduces pipe pressure. Although it does require a second register, given that this is a (cheap) zero register the impact is minimal. Differential Revision: https://reviews.llvm.org/D32973 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302525 91177308-0d34-0410-b5e6-96231b3b80d8