Richard Trieu d1fe8d5212 Change assert(0 && "text") to llvm_unreachable(0 && "text") ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185243 91177308-0d34-0410-b5e6-96231b3b80d8

2013-06-28 23:46:19 +00:00

..

InstPrinter

Change assert(0 && "text") to llvm_unreachable(0 && "text")

2013-06-28 23:46:19 +00:00

MCTargetDesc

Remove the MachineMove class.

2013-05-13 01:16:13 +00:00

TargetInfo

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CMakeLists.txt

Hexagon: Pass to replace tranfer/copy instructions into combine instruction

2013-05-14 18:54:06 +00:00

Hexagon.h

Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.

2013-06-19 21:36:55 +00:00

Hexagon.td

Hexagon: Fix switch statements in GetDotOldOp and IsNewifyStore.

2013-05-10 20:58:11 +00:00

HexagonAsmPrinter.cpp

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HexagonAsmPrinter.h

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HexagonCallingConv.td

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HexagonCallingConvLower.cpp

Don't cache the instruction and register info from the TargetMachine, because

2013-06-07 06:19:56 +00:00

HexagonCallingConvLower.h

Don't cache the instruction and register info from the TargetMachine, because

2013-06-07 06:19:56 +00:00

HexagonCFGOptimizer.cpp

Print IR from Hexagon MI passes with -print-before/after-all.

2013-05-06 21:58:00 +00:00

HexagonCopyToCombine.cpp

Hexagon: Typo fix.

2013-05-28 19:01:45 +00:00

HexagonExpandPredSpillCode.cpp

Print IR from Hexagon MI passes with -print-before/after-all.

2013-05-06 21:58:00 +00:00

HexagonFixupHwLoops.cpp

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HexagonFrameLowering.cpp

Remove dead calls to addFrameMove.

2013-05-16 15:08:37 +00:00

HexagonFrameLowering.h

Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo

2013-02-21 20:05:00 +00:00

HexagonHardwareLoops.cpp

Hexagon: Use multiclass for Jump instructions.

2013-05-01 21:37:34 +00:00

HexagonInstrFormats.td

Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.

2013-05-10 20:27:34 +00:00

HexagonInstrFormatsV4.td

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HexagonInstrInfo.cpp

DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs

2013-06-16 20:34:27 +00:00

HexagonInstrInfo.h

DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs

2013-06-16 20:34:27 +00:00

HexagonInstrInfo.td

Hexagon: Pass to replace tranfer/copy instructions into combine instruction

2013-05-14 18:54:06 +00:00

HexagonInstrInfoV3.td

Hexagon: Use multiclass for Jump instructions.

2013-05-01 21:37:34 +00:00

HexagonInstrInfoV4.td

Hexagon: Add patterns to generate 'combine' instructions.

2013-05-14 17:16:38 +00:00

HexagonInstrInfoV5.td

Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.

2013-05-10 20:27:34 +00:00

HexagonIntrinsics.td

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HexagonIntrinsicsDerived.td

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HexagonIntrinsicsV3.td

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HexagonIntrinsicsV4.td

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HexagonIntrinsicsV5.td

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HexagonISelDAGToDAG.cpp

Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.

2013-06-19 21:36:55 +00:00

HexagonISelLowering.cpp

The getRegForInlineAsmConstraint function should only accept MVT value types.

2013-06-22 18:37:38 +00:00

HexagonISelLowering.h

The getRegForInlineAsmConstraint function should only accept MVT value types.

2013-06-22 18:37:38 +00:00

HexagonMachineFunctionInfo.h

Hexagon: Use multiclass for Jump instructions.

2013-05-01 21:37:34 +00:00

HexagonMachineScheduler.cpp

Machine Model: Add MicroOpBufferSize and resource BufferSize.

2013-06-15 04:49:57 +00:00

HexagonMachineScheduler.h

Don't cache the instruction and register info from the TargetMachine, because

2013-06-07 06:19:56 +00:00

HexagonMCInstLower.cpp

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HexagonNewValueJump.cpp

Suppress GCC compiler warnings in release builds about variables that are only

2013-05-13 07:50:47 +00:00

HexagonOperands.td

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HexagonPeephole.cpp

Print IR from Hexagon MI passes with -print-before/after-all.

2013-05-06 21:58:00 +00:00

HexagonRegisterInfo.cpp

Don't cache the instruction and register info from the TargetMachine, because

2013-06-07 06:19:56 +00:00

HexagonRegisterInfo.h

Don't cache the instruction and register info from the TargetMachine, because

2013-06-07 06:19:56 +00:00

HexagonRegisterInfo.td

Make SubRegIndex size mandatory, following r183020.

2013-05-31 23:45:26 +00:00

HexagonRemoveSZExtArgs.cpp

Print IR from Hexagon MI passes with -print-before/after-all.

2013-05-06 21:58:00 +00:00

HexagonSchedule.td

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HexagonScheduleV4.td

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HexagonSelectCCInfo.td

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HexagonSelectionDAGInfo.cpp

Track IR ordering of SelectionDAG nodes 2/4.

2013-05-25 02:42:55 +00:00

HexagonSelectionDAGInfo.h

Track IR ordering of SelectionDAG nodes 2/4.

2013-05-25 02:42:55 +00:00

HexagonSplitConst32AndConst64.cpp

Hexagon: Fix Small Data support to handle -G 0 correctly.

2013-05-07 19:53:00 +00:00

HexagonSplitTFRCondSets.cpp

Print IR from Hexagon MI passes with -print-before/after-all.

2013-05-06 21:58:00 +00:00

HexagonSubtarget.cpp

Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and word.

2013-03-22 18:41:34 +00:00

HexagonSubtarget.h

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HexagonTargetMachine.cpp

Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.

2013-06-19 21:36:55 +00:00

HexagonTargetMachine.h

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HexagonTargetObjectFile.cpp

Hexagon: Fix Small Data support to handle -G 0 correctly.

2013-05-07 19:53:00 +00:00

HexagonTargetObjectFile.h

Hexagon: Fix Small Data support to handle -G 0 correctly.

2013-05-07 19:53:00 +00:00

HexagonVarargsCallingConvention.h

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HexagonVLIWPacketizer.cpp

Hexagon: Make helper functions static.

2013-05-23 15:43:11 +00:00

LLVMBuild.txt

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Makefile

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