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llvm/test/Transforms/SLPVectorizer
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Simon Pilgrim fb4c141673 [CostModel][X86] Improve sum reduction costs. 
I can't see any notable differences in costs between SSE2 and SSE42 arches for FADD/ADD reduction, so I've lowered the target to just SSE2.

I've also added vXi8 sum reduction costs in line with the PSADBW codegen and discussions on PR42674.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@374655 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-12 13:21:50 +00:00
..
AArch64
[SLP] respect target register width for GEP vectorization (PR43578)
2019-10-09 16:32:49 +00:00
AMDGPU
[LAA] Re-check bit-width of pointers after stripping.
2019-07-18 17:30:27 +00:00
ARM
Revert "Temporarily Revert "Add basic loop fusion pass.""
2019-04-17 04:52:47 +00:00
NVPTX
Revert "Temporarily Revert "Add basic loop fusion pass.""
2019-04-17 04:52:47 +00:00
PowerPC
Revert "Temporarily Revert "Add basic loop fusion pass.""
2019-04-17 04:52:47 +00:00
SystemZ
[lit] Delete empty lines at the end of lit.local.cfg NFC
2019-06-17 09:51:07 +00:00
X86
[CostModel][X86] Improve sum reduction costs.
2019-10-12 13:21:50 +00:00
XCore
Revert "Temporarily Revert "Add basic loop fusion pass.""
2019-04-17 04:52:47 +00:00
int_sideeffect.ll
Revert "Temporarily Revert "Add basic loop fusion pass.""
2019-04-17 04:52:47 +00:00