mirror of
https://github.com/RPCS3/llvm.git
synced 2025-04-06 15:21:37 +00:00
d39c38d2bc
Switch to MC for instruction printing. This encompasses several changes which are all interconnected: - Use the MC framework for printing almost all instructions. - AsmStrings are now live. - This introduces an indirection between LLVM vregs and WebAssembly registers, and a new pass, WebAssemblyRegNumbering, for computing a basic the mapping. This addresses some basic issues with argument registers and unused registers. - The way ARGUMENT instructions are handled no longer generates redundant get_local+set_local for every argument. This also changes the assembly syntax somewhat; most notably, MC's printing does not use sigils on label names, so those are no longer present, and push/pop now have a sigil to keep them unambiguous. The usage of set_local/get_local/$push/$pop will continue to evolve significantly. This patch is just one step of a larger change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252910 91177308-0d34-0410-b5e6-96231b3b80d8
97 lines
2.3 KiB
LLVM
97 lines
2.3 KiB
LLVM
; RUN: llc < %s -asm-verbose=false | FileCheck %s
|
|
|
|
; Test that extending loads are assembled properly.
|
|
|
|
target datalayout = "e-p:32:32-i64:64-n32:64-S128"
|
|
target triple = "wasm32-unknown-unknown"
|
|
|
|
; CHECK-LABEL: sext_i8_i32:
|
|
; CHECK: i32.load8_s $push, (get_local 0){{$}}
|
|
; CHECK-NEXT: set_local 1, $pop{{$}}
|
|
define i32 @sext_i8_i32(i8 *%p) {
|
|
%v = load i8, i8* %p
|
|
%e = sext i8 %v to i32
|
|
ret i32 %e
|
|
}
|
|
|
|
; CHECK-LABEL: zext_i8_i32:
|
|
; CHECK: i32.load8_u $push, (get_local 0){{$}}
|
|
; CHECK-NEXT: set_local 1, $pop{{$}}
|
|
define i32 @zext_i8_i32(i8 *%p) {
|
|
%v = load i8, i8* %p
|
|
%e = zext i8 %v to i32
|
|
ret i32 %e
|
|
}
|
|
|
|
; CHECK-LABEL: sext_i16_i32:
|
|
; CHECK: i32.load16_s $push, (get_local 0){{$}}
|
|
; CHECK-NEXT: set_local 1, $pop{{$}}
|
|
define i32 @sext_i16_i32(i16 *%p) {
|
|
%v = load i16, i16* %p
|
|
%e = sext i16 %v to i32
|
|
ret i32 %e
|
|
}
|
|
|
|
; CHECK-LABEL: zext_i16_i32:
|
|
; CHECK: i32.load16_u $push, (get_local 0){{$}}
|
|
; CHECK-NEXT: set_local 1, $pop{{$}}
|
|
define i32 @zext_i16_i32(i16 *%p) {
|
|
%v = load i16, i16* %p
|
|
%e = zext i16 %v to i32
|
|
ret i32 %e
|
|
}
|
|
|
|
; CHECK-LABEL: sext_i8_i64:
|
|
; CHECK: i64.load8_s $push, (get_local 0){{$}}
|
|
; CHECK-NEXT: set_local 1, $pop{{$}}
|
|
define i64 @sext_i8_i64(i8 *%p) {
|
|
%v = load i8, i8* %p
|
|
%e = sext i8 %v to i64
|
|
ret i64 %e
|
|
}
|
|
|
|
; CHECK-LABEL: zext_i8_i64:
|
|
; CHECK: i64.load8_u $push, (get_local 0){{$}}
|
|
; CHECK-NEXT: set_local 1, $pop{{$}}
|
|
define i64 @zext_i8_i64(i8 *%p) {
|
|
%v = load i8, i8* %p
|
|
%e = zext i8 %v to i64
|
|
ret i64 %e
|
|
}
|
|
|
|
; CHECK-LABEL: sext_i16_i64:
|
|
; CHECK: i64.load16_s $push, (get_local 0){{$}}
|
|
; CHECK-NEXT: set_local 1, $pop{{$}}
|
|
define i64 @sext_i16_i64(i16 *%p) {
|
|
%v = load i16, i16* %p
|
|
%e = sext i16 %v to i64
|
|
ret i64 %e
|
|
}
|
|
|
|
; CHECK-LABEL: zext_i16_i64:
|
|
; CHECK: i64.load16_u $push, (get_local 0){{$}}
|
|
; CHECK-NEXT: set_local 1, $pop{{$}}
|
|
define i64 @zext_i16_i64(i16 *%p) {
|
|
%v = load i16, i16* %p
|
|
%e = zext i16 %v to i64
|
|
ret i64 %e
|
|
}
|
|
|
|
; CHECK-LABEL: sext_i32_i64:
|
|
; CHECK: i64.load32_s $push, (get_local 0){{$}}
|
|
; CHECK-NEXT: set_local 1, $pop{{$}}
|
|
define i64 @sext_i32_i64(i32 *%p) {
|
|
%v = load i32, i32* %p
|
|
%e = sext i32 %v to i64
|
|
ret i64 %e
|
|
}
|
|
|
|
; CHECK-LABEL: zext_i32_i64:
|
|
; CHECK: i64.load32_u $push, (get_local 0){{$}}
|
|
; CHECK: set_local 1, $pop{{$}}
|
|
define i64 @zext_i32_i64(i32 *%p) {
|
|
%v = load i32, i32* %p
|
|
%e = zext i32 %v to i64
|
|
ret i64 %e
|
|
}
|