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A common coalescing conflict in vector code is lane insertion: %dst = FOO %src = BAR %dst:ssub0 = COPY %src The live range of %src interferes with the ssub0 lane of %dst, but that lane is never read after %src would have clobbered it. That makes it safe to merge the live ranges and eliminate the COPY: %dst = FOO %dst:ssub0 = BAR This patch teaches the new coalescer to resolve conflicts where dead vector lanes would be clobbered, at least as long as the clobbered vector lanes don't escape the basic block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164250 91177308-0d34-0410-b5e6-96231b3b80d8
144 lines
5.5 KiB
LLVM
144 lines
5.5 KiB
LLVM
; RUN: llc < %s -mcpu=cortex-a9 -new-coalescer | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
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target triple = "thumbv7-apple-ios0.0.0"
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; CHECK: f
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; The vld2 and vst2 are not aligned wrt each other, the second Q loaded is the
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; first one stored.
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; The coalescer must find a super-register larger than QQ to eliminate the copy
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; setting up the vst2 data.
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; CHECK: vld2
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; CHECK-NOT: vorr
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; CHECK-NOT: vmov
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; CHECK: vst2
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define void @f(float* %p, i32 %c) nounwind ssp {
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entry:
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%0 = bitcast float* %p to i8*
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%vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4)
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%vld221 = extractvalue { <4 x float>, <4 x float> } %vld2, 1
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%add.ptr = getelementptr inbounds float* %p, i32 8
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%1 = bitcast float* %add.ptr to i8*
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tail call void @llvm.arm.neon.vst2.v4f32(i8* %1, <4 x float> %vld221, <4 x float> undef, i32 4)
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ret void
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}
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; CHECK: f1
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; FIXME: This function still has copies.
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define void @f1(float* %p, i32 %c) nounwind ssp {
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entry:
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%0 = bitcast float* %p to i8*
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%vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4)
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%vld221 = extractvalue { <4 x float>, <4 x float> } %vld2, 1
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%add.ptr = getelementptr inbounds float* %p, i32 8
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%1 = bitcast float* %add.ptr to i8*
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%vld22 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %1, i32 4)
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%vld2215 = extractvalue { <4 x float>, <4 x float> } %vld22, 0
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tail call void @llvm.arm.neon.vst2.v4f32(i8* %1, <4 x float> %vld221, <4 x float> %vld2215, i32 4)
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ret void
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}
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; CHECK: f2
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; FIXME: This function still has copies.
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define void @f2(float* %p, i32 %c) nounwind ssp {
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entry:
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%0 = bitcast float* %p to i8*
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%vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4)
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%vld224 = extractvalue { <4 x float>, <4 x float> } %vld2, 1
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br label %do.body
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do.body: ; preds = %do.body, %entry
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%qq0.0.1.0 = phi <4 x float> [ %vld224, %entry ], [ %vld2216, %do.body ]
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%c.addr.0 = phi i32 [ %c, %entry ], [ %dec, %do.body ]
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%p.addr.0 = phi float* [ %p, %entry ], [ %add.ptr, %do.body ]
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%add.ptr = getelementptr inbounds float* %p.addr.0, i32 8
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%1 = bitcast float* %add.ptr to i8*
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%vld22 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %1, i32 4)
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%vld2215 = extractvalue { <4 x float>, <4 x float> } %vld22, 0
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%vld2216 = extractvalue { <4 x float>, <4 x float> } %vld22, 1
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tail call void @llvm.arm.neon.vst2.v4f32(i8* %1, <4 x float> %qq0.0.1.0, <4 x float> %vld2215, i32 4)
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%dec = add nsw i32 %c.addr.0, -1
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%tobool = icmp eq i32 %dec, 0
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br i1 %tobool, label %do.end, label %do.body
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do.end: ; preds = %do.body
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ret void
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}
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declare { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8*, i32) nounwind readonly
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declare void @llvm.arm.neon.vst2.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind
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; CHECK: f3
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; This function has lane insertions that span basic blocks.
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; The trivial REG_SEQUENCE lowering can't handle that, but the coalescer can.
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;
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; void f3(float *p, float *q) {
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; float32x2_t x;
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; x[1] = p[3];
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; if (q)
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; x[0] = q[0] + q[1];
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; else
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; x[0] = p[2];
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; vst1_f32(p+4, x);
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; }
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;
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; CHECK-NOT: vmov
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; CHECK-NOT: vorr
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define void @f3(float* %p, float* %q) nounwind ssp {
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entry:
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%arrayidx = getelementptr inbounds float* %p, i32 3
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%0 = load float* %arrayidx, align 4
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%vecins = insertelement <2 x float> undef, float %0, i32 1
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%tobool = icmp eq float* %q, null
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br i1 %tobool, label %if.else, label %if.then
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if.then: ; preds = %entry
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%1 = load float* %q, align 4
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%arrayidx2 = getelementptr inbounds float* %q, i32 1
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%2 = load float* %arrayidx2, align 4
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%add = fadd float %1, %2
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%vecins3 = insertelement <2 x float> %vecins, float %add, i32 0
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br label %if.end
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if.else: ; preds = %entry
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%arrayidx4 = getelementptr inbounds float* %p, i32 2
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%3 = load float* %arrayidx4, align 4
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%vecins5 = insertelement <2 x float> %vecins, float %3, i32 0
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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%x.0 = phi <2 x float> [ %vecins3, %if.then ], [ %vecins5, %if.else ]
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%add.ptr = getelementptr inbounds float* %p, i32 4
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%4 = bitcast float* %add.ptr to i8*
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tail call void @llvm.arm.neon.vst1.v2f32(i8* %4, <2 x float> %x.0, i32 4)
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ret void
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}
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declare void @llvm.arm.neon.vst1.v2f32(i8*, <2 x float>, i32) nounwind
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declare <2 x float> @llvm.arm.neon.vld1.v2f32(i8*, i32) nounwind readonly
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; CHECK: f4
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; This function inserts a lane into a fully defined vector.
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; The destination lane isn't read, so the subregs can coalesce.
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; CHECK-NOT: vmov
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; CHECK-NOT: vorr
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define void @f4(float* %p, float* %q) nounwind ssp {
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entry:
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%0 = bitcast float* %p to i8*
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%vld1 = tail call <2 x float> @llvm.arm.neon.vld1.v2f32(i8* %0, i32 4)
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%tobool = icmp eq float* %q, null
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br i1 %tobool, label %if.end, label %if.then
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if.then: ; preds = %entry
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%1 = load float* %q, align 4
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%arrayidx1 = getelementptr inbounds float* %q, i32 1
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%2 = load float* %arrayidx1, align 4
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%add = fadd float %1, %2
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%vecins = insertelement <2 x float> %vld1, float %add, i32 1
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br label %if.end
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if.end: ; preds = %entry, %if.then
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%x.0 = phi <2 x float> [ %vecins, %if.then ], [ %vld1, %entry ]
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tail call void @llvm.arm.neon.vst1.v2f32(i8* %0, <2 x float> %x.0, i32 4)
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ret void
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}
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