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Since r279760, we've been marking as legal operations on narrow integer types that have wider legal equivalents (for instance, G_ADD s8). Compared to legalizing these operations, this reduced the amount of extends/truncates required, but was always a weird legalization decision made at selection time. So far, we haven't been able to formalize it in a way that permits the selector generated from SelectionDAG patterns to be sufficient. Using a wide instruction (say, s64), when a narrower instruction exists (s32) would introduce register class incompatibilities (when one narrow generic instruction is selected to the wider variant, but another is selected to the narrower variant). It's also impractical to limit which narrow operations are matched for which instruction, as restricting "narrow selection" to ranges of types clashes with potentially incompatible instruction predicates. Concerns were also raised regarding MIPS64's sign-extended register assumptions, as well as wrapping behavior. See discussions in https://reviews.llvm.org/D26878. Instead, legalize the operations. Should we ever revert to selecting these narrow operations, we should try to represent this more accurately: for instance, by separating a "concrete" type on operations, and an "underlying" type on vregs, we could move the "this narrow-looking op is really legal" decision to the legalizer, and let the selector use the "underlying" vreg type only, which would be guaranteed to map to a register class. In any case, we eventually should mitigate: - the performance impact by selecting no-op extract/truncates to COPYs (which we currently do), and the COPYs to register reuses (which we don't do yet). - the compile-time impact by optimizing away extract/truncate sequences in the legalizer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292827 91177308-0d34-0410-b5e6-96231b3b80d8
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============================
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Global Instruction Selection
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============================
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.. contents::
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:local:
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:depth: 1
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.. warning::
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This document is a work in progress. It reflects the current state of the
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implementation, as well as open design and implementation issues.
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Introduction
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============
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GlobalISel is a framework that provides a set of reusable passes and utilities
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for instruction selection --- translation from LLVM IR to target-specific
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Machine IR (MIR).
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GlobalISel is intended to be a replacement for SelectionDAG and FastISel, to
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solve three major problems:
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* **Performance** --- SelectionDAG introduces a dedicated intermediate
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representation, which has a compile-time cost.
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GlobalISel directly operates on the post-isel representation used by the
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rest of the code generator, MIR.
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It does require extensions to that representation to support arbitrary
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incoming IR: :ref:`gmir`.
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* **Granularity** --- SelectionDAG and FastISel operate on individual basic
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blocks, losing some global optimization opportunities.
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GlobalISel operates on the whole function.
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* **Modularity** --- SelectionDAG and FastISel are radically different and share
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very little code.
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GlobalISel is built in a way that enables code reuse. For instance, both the
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optimized and fast selectors share the :ref:`pipeline`, and targets can
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configure that pipeline to better suit their needs.
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.. _gmir:
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Generic Machine IR
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==================
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Machine IR operates on physical registers, register classes, and (mostly)
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target-specific instructions.
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To bridge the gap with LLVM IR, GlobalISel introduces "generic" extensions to
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Machine IR:
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.. contents::
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:local:
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``NOTE``:
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The generic MIR (GMIR) representation still contains references to IR
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constructs (such as ``GlobalValue``). Removing those should let us write more
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accurate tests, or delete IR after building the initial MIR. However, it is
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not part of the GlobalISel effort.
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.. _gmir-instructions:
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Generic Instructions
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--------------------
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The main addition is support for pre-isel generic machine instructions (e.g.,
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``G_ADD``). Like other target-independent instructions (e.g., ``COPY`` or
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``PHI``), these are available on all targets.
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``TODO``:
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While we're progressively adding instructions, one kind in particular exposes
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interesting problems: compares and how to represent condition codes.
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Some targets (x86, ARM) have generic comparisons setting multiple flags,
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which are then used by predicated variants.
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Others (IR) specify the predicate in the comparison and users just get a single
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bit. SelectionDAG uses SETCC/CONDBR vs BR_CC (and similar for select) to
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represent this.
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The ``MachineIRBuilder`` class wraps the ``MachineInstrBuilder`` and provides
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a convenient way to create these generic instructions.
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.. _gmir-gvregs:
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Generic Virtual Registers
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-------------------------
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Generic instructions operate on a new kind of register: "generic" virtual
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registers. As opposed to non-generic vregs, they are not assigned a Register
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Class. Instead, generic vregs have a :ref:`gmir-llt`, and can be assigned
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a :ref:`gmir-regbank`.
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``MachineRegisterInfo`` tracks the same information that it does for
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non-generic vregs (e.g., use-def chains). Additionally, it also tracks the
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:ref:`gmir-llt` of the register, and, instead of the ``TargetRegisterClass``,
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its :ref:`gmir-regbank`, if any.
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For simplicity, most generic instructions only accept generic vregs:
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* instead of immediates, they use a gvreg defined by an instruction
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materializing the immediate value (see :ref:`irtranslator-constants`).
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* instead of physical register, they use a gvreg defined by a ``COPY``.
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``NOTE``:
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We started with an alternative representation, where MRI tracks a size for
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each gvreg, and instructions have lists of types.
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That had two flaws: the type and size are redundant, and there was no generic
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way of getting a given operand's type (as there was no 1:1 mapping between
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instruction types and operands).
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We considered putting the type in some variant of MCInstrDesc instead:
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See `PR26576 <http://llvm.org/PR26576>`_: [GlobalISel] Generic MachineInstrs
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need a type but this increases the memory footprint of the related objects
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.. _gmir-regbank:
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Register Bank
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-------------
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A Register Bank is a set of register classes defined by the target.
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A bank has a size, which is the maximum store size of all covered classes.
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In general, cross-class copies inside a bank are expected to be cheaper than
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copies across banks. They are also coalesceable by the register coalescer,
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whereas cross-bank copies are not.
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Also, equivalent operations can be performed on different banks using different
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instructions.
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For example, X86 can be seen as having 3 main banks: general-purpose, x87, and
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vector (which could be further split into a bank per domain for single vs
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double precision instructions).
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Register banks are described by a target-provided API,
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:ref:`RegisterBankInfo <api-registerbankinfo>`.
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.. _gmir-llt:
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Low Level Type
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--------------
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Additionally, every generic virtual register has a type, represented by an
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instance of the ``LLT`` class.
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Like ``EVT``/``MVT``/``Type``, it has no distinction between unsigned and signed
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integer types. Furthermore, it also has no distinction between integer and
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floating-point types: it mainly conveys absolutely necessary information, such
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as size and number of vector lanes:
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* ``sN`` for scalars
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* ``pN`` for pointers
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* ``<N x sM>`` for vectors
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* ``unsized`` for labels, etc..
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``LLT`` is intended to replace the usage of ``EVT`` in SelectionDAG.
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Here are some LLT examples and their ``EVT`` and ``Type`` equivalents:
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============= ========= ======================================
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LLT EVT IR Type
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============= ========= ======================================
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``s1`` ``i1`` ``i1``
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``s8`` ``i8`` ``i8``
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``s32`` ``i32`` ``i32``
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``s32`` ``f32`` ``float``
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``s17`` ``i17`` ``i17``
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``s16`` N/A ``{i8, i8}``
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``s32`` N/A ``[4 x i8]``
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``p0`` ``iPTR`` ``i8*``, ``i32*``, ``%opaque*``
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``p2`` ``iPTR`` ``i8 addrspace(2)*``
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``<4 x s32>`` ``v4f32`` ``<4 x float>``
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``s64`` ``v1f64`` ``<1 x double>``
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``<3 x s32>`` ``v3i32`` ``<3 x i32>``
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``unsized`` ``Other`` ``label``
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============= ========= ======================================
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Rationale: instructions already encode a specific interpretation of types
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(e.g., ``add`` vs. ``fadd``, or ``sdiv`` vs. ``udiv``). Also encoding that
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information in the type system requires introducing bitcast with no real
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advantage for the selector.
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Pointer types are distinguished by address space. This matches IR, as opposed
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to SelectionDAG where address space is an attribute on operations.
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This representation better supports pointers having different sizes depending
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on their addressspace.
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``NOTE``:
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Currently, LLT requires at least 2 elements in vectors, but some targets have
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the concept of a '1-element vector'. Representing them as their underlying
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scalar type is a nice simplification.
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``TODO``:
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Currently, non-generic virtual registers, defined by non-pre-isel-generic
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instructions, cannot have a type, and thus cannot be used by a pre-isel generic
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instruction. Instead, they are given a type using a COPY. We could relax that
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and allow types on all vregs: this would reduce the number of MI required when
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emitting target-specific MIR early in the pipeline. This should purely be
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a compile-time optimization.
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.. _pipeline:
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Core Pipeline
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=============
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There are four required passes, regardless of the optimization mode:
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.. contents::
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:local:
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Additional passes can then be inserted at higher optimization levels or for
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specific targets. For example, to match the current SelectionDAG set of
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transformations: MachineCSE and a better MachineCombiner between every pass.
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``NOTE``:
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In theory, not all passes are always necessary.
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As an additional compile-time optimization, we could skip some of the passes by
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setting the relevant MachineFunction properties. For instance, if the
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IRTranslator did not encounter any illegal instruction, it would set the
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``legalized`` property to avoid running the :ref:`milegalizer`.
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Similarly, we considered specializing the IRTranslator per-target to directly
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emit target-specific MI.
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However, we instead decided to keep the core pipeline simple, and focus on
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minimizing the overhead of the passes in the no-op cases.
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.. _irtranslator:
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IRTranslator
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------------
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This pass translates the input LLVM IR ``Function`` to a GMIR
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``MachineFunction``.
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``TODO``:
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This currently doesn't support the more complex instructions, in particular
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those involving control flow (``switch``, ``invoke``, ...).
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For ``switch`` in particular, we can initially use the ``LowerSwitch`` pass.
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.. _api-calllowering:
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API: CallLowering
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^^^^^^^^^^^^^^^^^
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The ``IRTranslator`` (using the ``CallLowering`` target-provided utility) also
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implements the ABI's calling convention by lowering calls, returns, and
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arguments to the appropriate physical register usage and instruction sequences.
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.. _irtranslator-aggregates:
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Aggregates
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^^^^^^^^^^
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Aggregates are lowered to a single scalar vreg.
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This differs from SelectionDAG's multiple vregs via ``GetValueVTs``.
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``TODO``:
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As some of the bits are undef (padding), we should consider augmenting the
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representation with additional metadata (in effect, caching computeKnownBits
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information on vregs).
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See `PR26161 <http://llvm.org/PR26161>`_: [GlobalISel] Value to vreg during
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IR to MachineInstr translation for aggregate type
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.. _irtranslator-constants:
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Constant Lowering
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^^^^^^^^^^^^^^^^^
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The ``IRTranslator`` lowers ``Constant`` operands into uses of gvregs defined
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by ``G_CONSTANT`` or ``G_FCONSTANT`` instructions.
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Currently, these instructions are always emitted in the entry basic block.
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In a ``MachineFunction``, each ``Constant`` is materialized by a single gvreg.
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This is beneficial as it allows us to fold constants into immediate operands
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during :ref:`instructionselect`, while still avoiding redundant materializations
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for expensive non-foldable constants.
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However, this can lead to unnecessary spills and reloads in an -O0 pipeline, as
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these vregs can have long live ranges.
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``TODO``:
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We're investigating better placement of these instructions, in fast and
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optimized modes.
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.. _milegalizer:
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Legalizer
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---------
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This pass transforms the generic machine instructions such that they are legal.
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A legal instruction is defined as:
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* **selectable** --- the target will later be able to select it to a
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target-specific (non-generic) instruction.
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* operating on **vregs that can be loaded and stored** -- if necessary, the
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target can select a ``G_LOAD``/``G_STORE`` of each gvreg operand.
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As opposed to SelectionDAG, there are no legalization phases. In particular,
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'type' and 'operation' legalization are not separate.
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Legalization is iterative, and all state is contained in GMIR. To maintain the
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validity of the intermediate code, instructions are introduced:
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* ``G_SEQUENCE`` --- concatenate multiple registers into a single wider
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register.
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* ``G_EXTRACT`` --- extract multiple registers (as contiguous sequences of bits)
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from a single wider register.
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As they are expected to be temporary byproducts of the legalization process,
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they are combined at the end of the :ref:`milegalizer` pass.
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If any remain, they are expected to always be selectable, using loads and stores
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if necessary.
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.. _api-legalizerinfo:
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API: LegalizerInfo
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^^^^^^^^^^^^^^^^^^
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Currently the API is broadly similar to SelectionDAG/TargetLowering, but
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extended in two ways:
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* The set of available actions is wider, avoiding the currently very
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overloaded ``Expand`` (which can cover everything from libcalls to
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scalarization depending on the node's opcode).
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* Since there's no separate type legalization, independently varying
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types on an instruction can have independent actions. For example a
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``G_ICMP`` has 2 independent types: the result and the inputs; we need
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to be able to say that comparing 2 s32s is OK, but the s1 result
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must be dealt with in another way.
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As such, the primary key when deciding what to do is the ``InstrAspect``,
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essentially a tuple consisting of ``(Opcode, TypeIdx, Type)`` and mapping to a
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suggested course of action.
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An example use might be:
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.. code-block:: c++
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// The CPU can't deal with an s1 result, do something about it.
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setAction({G_ICMP, 0, s1}, WidenScalar);
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// An s32 input (the second type) is fine though.
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setAction({G_ICMP, 1, s32}, Legal);
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``TODO``:
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An alternative worth investigating is to generalize the API to represent
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actions using ``std::function`` that implements the action, instead of explicit
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enum tokens (``Legal``, ``WidenScalar``, ...).
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``TODO``:
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Moreover, we could use TableGen to initially infer legality of operation from
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existing patterns (as any pattern we can select is by definition legal).
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Expanding that to describe legalization actions is a much larger but
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potentially useful project.
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.. _milegalizer-non-power-of-2:
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Non-power of 2 types
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^^^^^^^^^^^^^^^^^^^^
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``TODO``:
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Types which have a size that isn't a power of 2 aren't currently supported.
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The setAction API will probably require changes to support them.
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Even notionally explicitly specified operations only make suggestions
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like "Widen" or "Narrow". The eventual type is still unspecified and a
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search is performed by repeated doubling/halving of the type's
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size.
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This is incorrect for types that aren't a power of 2. It's reasonable to
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expect we could construct an efficient set of side-tables for more general
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lookups though, encoding a map from the integers (i.e. the size of the current
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type) to types (the legal size).
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.. _milegalizer-vector:
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Vector types
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^^^^^^^^^^^^
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Vectors first get their element type legalized: ``<A x sB>`` becomes
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``<A x sC>`` such that at least one operation is legal with ``sC``.
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This is currently specified by the function ``setScalarInVectorAction``, called
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for example as:
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setScalarInVectorAction(G_ICMP, s1, WidenScalar);
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Next the number of elements is chosen so that the entire operation is
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legal. This aspect is not controllable at the moment, but probably
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should be (you could imagine disagreements on whether a ``<2 x s8>``
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operation should be scalarized or extended to ``<8 x s8>``).
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.. _regbankselect:
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RegBankSelect
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-------------
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This pass constrains the :ref:`gmir-gvregs` operands of generic
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instructions to some :ref:`gmir-regbank`.
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It iteratively maps instructions to a set of per-operand bank assignment.
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The possible mappings are determined by the target-provided
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:ref:`RegisterBankInfo <api-registerbankinfo>`.
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The mapping is then applied, possibly introducing ``COPY`` instructions if
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necessary.
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It traverses the ``MachineFunction`` top down so that all operands are already
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mapped when analyzing an instruction.
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This pass could also remap target-specific instructions when beneficial.
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In the future, this could replace the ExeDepsFix pass, as we can directly
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select the best variant for an instruction that's available on multiple banks.
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.. _api-registerbankinfo:
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API: RegisterBankInfo
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^^^^^^^^^^^^^^^^^^^^^
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The ``RegisterBankInfo`` class describes multiple aspects of register banks.
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* **Banks**: ``addRegBankCoverage`` --- which register bank covers each
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register class.
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* **Cross-Bank Copies**: ``copyCost`` --- the cost of a ``COPY`` from one bank
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to another.
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* **Default Mapping**: ``getInstrMapping`` --- the default bank assignments for
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a given instruction.
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* **Alternative Mapping**: ``getInstrAlternativeMapping`` --- the other
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possible bank assignments for a given instruction.
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``TODO``:
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All this information should eventually be static and generated by TableGen,
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mostly using existing information augmented by bank descriptions.
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``TODO``:
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``getInstrMapping`` is currently separate from ``getInstrAlternativeMapping``
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because the latter is more expensive: as we move to static mapping info,
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both methods should be free, and we should merge them.
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.. _regbankselect-modes:
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RegBankSelect Modes
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^^^^^^^^^^^^^^^^^^^
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``RegBankSelect`` currently has two modes:
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* **Fast** --- For each instruction, pick a target-provided "default" bank
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assignment. This is the default at -O0.
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* **Greedy** --- For each instruction, pick the cheapest of several
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target-provided bank assignment alternatives.
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We intend to eventually introduce an additional optimizing mode:
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* **Global** --- Across multiple instructions, pick the cheapest combination of
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bank assignments.
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``NOTE``:
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On AArch64, we are considering using the Greedy mode even at -O0 (or perhaps at
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backend -O1): because :ref:`gmir-llt` doesn't distinguish floating point from
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integer scalars, the default assignment for loads and stores is the integer
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bank, introducing cross-bank copies on most floating point operations.
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.. _instructionselect:
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InstructionSelect
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-----------------
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This pass transforms generic machine instructions into equivalent
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target-specific instructions. It traverses the ``MachineFunction`` bottom-up,
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selecting uses before definitions, enabling trivial dead code elimination.
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.. _api-instructionselector:
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API: InstructionSelector
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^^^^^^^^^^^^^^^^^^^^^^^^
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The target implements the ``InstructionSelector`` class, containing the
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target-specific selection logic proper.
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The instance is provided by the subtarget, so that it can specialize the
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selector by subtarget feature (with, e.g., a vector selector overriding parts
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of a general-purpose common selector).
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We might also want to parameterize it by MachineFunction, to enable selector
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variants based on function attributes like optsize.
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The simple API consists of:
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.. code-block:: c++
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virtual bool select(MachineInstr &MI)
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This target-provided method is responsible for mutating (or replacing) a
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possibly-generic MI into a fully target-specific equivalent.
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It is also responsible for doing the necessary constraining of gvregs into the
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appropriate register classes.
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The ``InstructionSelector`` can fold other instructions into the selected MI,
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by walking the use-def chain of the vreg operands.
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As GlobalISel is Global, this folding can occur across basic blocks.
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``TODO``:
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Currently, the Select pass is implemented with hand-written c++, similar to
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FastISel, rather than backed by tblgen'erated pattern-matching.
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We intend to eventually reuse SelectionDAG patterns.
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.. _maintainability:
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Maintainability
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===============
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.. _maintainability-iterative:
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Iterative Transformations
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-------------------------
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Passes are split into small, iterative transformations, with all state
|
|
represented in the MIR.
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This differs from SelectionDAG (in particular, the legalizer) using various
|
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in-memory side-tables.
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.. _maintainability-mir:
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|
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|
MIR Serialization
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|
-----------------
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|
|
|
.. FIXME: Update the MIRLangRef to include GMI additions.
|
|
|
|
:ref:`gmir` is serializable (see :doc:`MIRLangRef`).
|
|
Combined with :ref:`maintainability-iterative`, this enables much finer-grained
|
|
testing, rather than requiring large and fragile IR-to-assembly tests.
|
|
|
|
The current "stage" in the :ref:`pipeline` is represented by a set of
|
|
``MachineFunctionProperties``:
|
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|
|
* ``legalized``
|
|
* ``regBankSelected``
|
|
* ``selected``
|
|
|
|
|
|
.. _maintainability-verifier:
|
|
|
|
MachineVerifier
|
|
---------------
|
|
|
|
The pass approach lets us use the ``MachineVerifier`` to enforce invariants.
|
|
For instance, a ``regBankSelected`` function may not have gvregs without
|
|
a bank.
|
|
|
|
``TODO``:
|
|
The ``MachineVerifier`` being monolithic, some of the checks we want to do
|
|
can't be integrated to it: GlobalISel is a separate library, so we can't
|
|
directly reference it from CodeGen. For instance, legality checks are
|
|
currently done in RegBankSelect/InstructionSelect proper. We could #ifdef out
|
|
the checks, or we could add some sort of verifier API.
|
|
|
|
|
|
.. _progress:
|
|
|
|
Progress and Future Work
|
|
========================
|
|
|
|
The initial goal is to replace FastISel on AArch64. The next step will be to
|
|
replace SelectionDAG as the optimized ISel.
|
|
|
|
``NOTE``:
|
|
While we iterate on GlobalISel, we strive to avoid affecting the performance of
|
|
SelectionDAG, FastISel, or the other MIR passes. For instance, the types of
|
|
:ref:`gmir-gvregs` are stored in a separate table in ``MachineRegisterInfo``,
|
|
that is destroyed after :ref:`instructionselect`.
|
|
|
|
.. _progress-fastisel:
|
|
|
|
FastISel Replacement
|
|
--------------------
|
|
|
|
For the initial FastISel replacement, we intend to fallback to SelectionDAG on
|
|
selection failures.
|
|
|
|
Currently, compile-time of the fast pipeline is within 1.5x of FastISel.
|
|
We're optimistic we can get to within 1.1/1.2x, but beating FastISel will be
|
|
challenging given the multi-pass approach.
|
|
Still, supporting all IR (via a complete legalizer) and avoiding the fallback
|
|
to SelectionDAG in the worst case should enable better amortized performance
|
|
than SelectionDAG+FastISel.
|
|
|
|
``NOTE``:
|
|
We considered never having a fallback to SelectionDAG, instead deciding early
|
|
whether a given function is supported by GlobalISel or not. The decision would
|
|
be based on :ref:`milegalizer` queries.
|
|
We abandoned that for two reasons:
|
|
a) on IR inputs, we'd need to basically simulate the :ref:`irtranslator`;
|
|
b) to be robust against unforeseen failures and to enable iterative
|
|
improvements.
|
|
|
|
.. _progress-targets:
|
|
|
|
Support For Other Targets
|
|
-------------------------
|
|
|
|
In parallel, we're investigating adding support for other - ideally quite
|
|
different - targets. For instance, there is some initial AMDGPU support.
|
|
|
|
|
|
.. _porting:
|
|
|
|
Porting GlobalISel to A New Target
|
|
==================================
|
|
|
|
There are four major classes to implement by the target:
|
|
|
|
* :ref:`CallLowering <api-calllowering>` --- lower calls, returns, and arguments
|
|
according to the ABI.
|
|
* :ref:`RegisterBankInfo <api-registerbankinfo>` --- describe
|
|
:ref:`gmir-regbank` coverage, cross-bank copy cost, and the mapping of
|
|
operands onto banks for each instruction.
|
|
* :ref:`LegalizerInfo <api-legalizerinfo>` --- describe what is legal, and how
|
|
to legalize what isn't.
|
|
* :ref:`InstructionSelector <api-instructionselector>` --- select generic MIR
|
|
to target-specific MIR.
|
|
|
|
Additionally:
|
|
|
|
* ``TargetPassConfig`` --- create the passes constituting the pipeline,
|
|
including additional passes not included in the :ref:`pipeline`.
|
|
* ``GISelAccessor`` --- setup the various subtarget-provided classes, with a
|
|
graceful fallback to no-op when GlobalISel isn't enabled.
|