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1cbca515b6
target independent.
Most of the x86 specific stackmap/patchpoint handling was necessitated by the
use of the native address-mode format for frame index operands. PEI has now
been modified to treat stackmap/patchpoint similarly to DEBUG_INFO, allowing
us to use a simple, platform independent register/offset pair for frame
indexes on stackmap/patchpoints.
Notes:
- Folding is now platform independent and automatically supported.
- Emiting patchpoints with direct memory references now just involves calling
the TargetLoweringBase::emitPatchPoint utility method from the target's
XXXTargetLowering::EmitInstrWithCustomInserter method. (See
X86TargetLowering for an example).
- No more ugly platform-specific operand parsers.
This patch shouldn't change the generated output for X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195944 91177308-0d34-0410-b5e6-96231b3b80d8
371 lines
13 KiB
C++
371 lines
13 KiB
C++
//===---------------------------- StackMaps.cpp ---------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "stackmaps"
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#include "llvm/CodeGen/StackMaps.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCObjectFileInfo.h"
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#include "llvm/MC/MCSectionMachO.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetOpcodes.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include <iterator>
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using namespace llvm;
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PatchPointOpers::PatchPointOpers(const MachineInstr *MI):
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MI(MI),
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HasDef(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
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!MI->getOperand(0).isImplicit()),
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IsAnyReg(MI->getOperand(getMetaIdx(CCPos)).getImm() == CallingConv::AnyReg) {
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#ifndef NDEBUG
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{
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unsigned CheckStartIdx = 0, e = MI->getNumOperands();
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while (CheckStartIdx < e && MI->getOperand(CheckStartIdx).isReg() &&
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MI->getOperand(CheckStartIdx).isDef() &&
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!MI->getOperand(CheckStartIdx).isImplicit())
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++CheckStartIdx;
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assert(getMetaIdx() == CheckStartIdx &&
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"Unexpected additonal definition in Patchpoint intrinsic.");
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}
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#endif
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}
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unsigned PatchPointOpers::getNextScratchIdx(unsigned StartIdx) const {
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if (!StartIdx)
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StartIdx = getVarIdx();
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// Find the next scratch register (implicit def and early clobber)
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unsigned ScratchIdx = StartIdx, e = MI->getNumOperands();
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while (ScratchIdx < e &&
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!(MI->getOperand(ScratchIdx).isReg() &&
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MI->getOperand(ScratchIdx).isDef() &&
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MI->getOperand(ScratchIdx).isImplicit() &&
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MI->getOperand(ScratchIdx).isEarlyClobber()))
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++ScratchIdx;
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assert(ScratchIdx != e && "No scratch register available");
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return ScratchIdx;
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}
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std::pair<StackMaps::Location, MachineInstr::const_mop_iterator>
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StackMaps::parseOperand(MachineInstr::const_mop_iterator MOI,
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MachineInstr::const_mop_iterator MOE) {
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const MachineOperand &MOP = *MOI;
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assert(!MOP.isRegMask() && (!MOP.isReg() || !MOP.isImplicit()) &&
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"Register mask and implicit operands should not be processed.");
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if (MOP.isImm()) {
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// Verify anyregcc
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// [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
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switch (MOP.getImm()) {
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default: llvm_unreachable("Unrecognized operand type.");
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case StackMaps::DirectMemRefOp: {
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unsigned Size = AP.TM.getDataLayout()->getPointerSizeInBits();
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assert((Size % 8) == 0 && "Need pointer size in bytes.");
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Size /= 8;
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unsigned Reg = (++MOI)->getReg();
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int64_t Imm = (++MOI)->getImm();
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return std::make_pair(
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Location(StackMaps::Location::Direct, Size, Reg, Imm), ++MOI);
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}
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case StackMaps::IndirectMemRefOp: {
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int64_t Size = (++MOI)->getImm();
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assert(Size > 0 && "Need a valid size for indirect memory locations.");
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unsigned Reg = (++MOI)->getReg();
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int64_t Imm = (++MOI)->getImm();
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return std::make_pair(
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Location(StackMaps::Location::Indirect, Size, Reg, Imm), ++MOI);
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}
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case StackMaps::ConstantOp: {
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++MOI;
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assert(MOI->isImm() && "Expected constant operand.");
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int64_t Imm = MOI->getImm();
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return std::make_pair(
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Location(Location::Constant, sizeof(int64_t), 0, Imm), ++MOI);
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}
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}
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}
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// Otherwise this is a reg operand. The physical register number will
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// ultimately be encoded as a DWARF regno. The stack map also records the size
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// of a spill slot that can hold the register content. (The runtime can
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// track the actual size of the data type if it needs to.)
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assert(MOP.isReg() && "Expected register operand here.");
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assert(TargetRegisterInfo::isPhysicalRegister(MOP.getReg()) &&
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"Virtreg operands should have been rewritten before now.");
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const TargetRegisterClass *RC =
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AP.TM.getRegisterInfo()->getMinimalPhysRegClass(MOP.getReg());
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assert(!MOP.getSubReg() && "Physical subreg still around.");
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return std::make_pair(
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Location(Location::Register, RC->getSize(), MOP.getReg(), 0), ++MOI);
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}
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void StackMaps::recordStackMapOpers(const MachineInstr &MI, uint32_t ID,
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MachineInstr::const_mop_iterator MOI,
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MachineInstr::const_mop_iterator MOE,
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bool recordResult) {
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MCContext &OutContext = AP.OutStreamer.getContext();
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MCSymbol *MILabel = OutContext.CreateTempSymbol();
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AP.OutStreamer.EmitLabel(MILabel);
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LocationVec CallsiteLocs;
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if (recordResult) {
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std::pair<Location, MachineInstr::const_mop_iterator> ParseResult =
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parseOperand(MI.operands_begin(), llvm::next(MI.operands_begin()));
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Location &Loc = ParseResult.first;
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assert(Loc.LocType == Location::Register &&
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"Stackmap return location must be a register.");
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CallsiteLocs.push_back(Loc);
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}
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while (MOI != MOE) {
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Location Loc;
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tie(Loc, MOI) = parseOperand(MOI, MOE);
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// Move large constants into the constant pool.
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if (Loc.LocType == Location::Constant && (Loc.Offset & ~0xFFFFFFFFULL)) {
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Loc.LocType = Location::ConstantIndex;
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Loc.Offset = ConstPool.getConstantIndex(Loc.Offset);
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}
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CallsiteLocs.push_back(Loc);
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}
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const MCExpr *CSOffsetExpr = MCBinaryExpr::CreateSub(
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MCSymbolRefExpr::Create(MILabel, OutContext),
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MCSymbolRefExpr::Create(AP.CurrentFnSym, OutContext),
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OutContext);
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CSInfos.push_back(CallsiteInfo(CSOffsetExpr, ID, CallsiteLocs));
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}
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static MachineInstr::const_mop_iterator
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getStackMapEndMOP(MachineInstr::const_mop_iterator MOI,
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MachineInstr::const_mop_iterator MOE) {
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for (; MOI != MOE; ++MOI)
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if (MOI->isRegMask() || (MOI->isReg() && MOI->isImplicit()))
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break;
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return MOI;
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}
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void StackMaps::recordStackMap(const MachineInstr &MI) {
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assert(MI.getOpcode() == TargetOpcode::STACKMAP && "exected stackmap");
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int64_t ID = MI.getOperand(0).getImm();
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assert((int32_t)ID == ID && "Stack maps hold 32-bit IDs");
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recordStackMapOpers(MI, ID, llvm::next(MI.operands_begin(), 2),
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getStackMapEndMOP(MI.operands_begin(),
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MI.operands_end()));
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}
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void StackMaps::recordPatchPoint(const MachineInstr &MI) {
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assert(MI.getOpcode() == TargetOpcode::PATCHPOINT && "exected stackmap");
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PatchPointOpers opers(&MI);
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int64_t ID = opers.getMetaOper(PatchPointOpers::IDPos).getImm();
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assert((int32_t)ID == ID && "Stack maps hold 32-bit IDs");
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MachineInstr::const_mop_iterator MOI =
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llvm::next(MI.operands_begin(), opers.getStackMapStartIdx());
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recordStackMapOpers(MI, ID, MOI, getStackMapEndMOP(MOI, MI.operands_end()),
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opers.isAnyReg() && opers.hasDef());
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#ifndef NDEBUG
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// verify anyregcc
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LocationVec &Locations = CSInfos.back().Locations;
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if (opers.isAnyReg()) {
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unsigned NArgs = opers.getMetaOper(PatchPointOpers::NArgPos).getImm();
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for (unsigned i = 0, e = (opers.hasDef() ? NArgs+1 : NArgs); i != e; ++i)
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assert(Locations[i].LocType == Location::Register &&
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"anyreg arg must be in reg.");
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}
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#endif
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}
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/// serializeToStackMapSection conceptually populates the following fields:
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///
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/// uint32 : Reserved (header)
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/// uint32 : NumConstants
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/// int64 : Constants[NumConstants]
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/// uint32 : NumRecords
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/// StkMapRecord[NumRecords] {
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/// uint32 : PatchPoint ID
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/// uint32 : Instruction Offset
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/// uint16 : Reserved (record flags)
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/// uint16 : NumLocations
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/// Location[NumLocations] {
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/// uint8 : Register | Direct | Indirect | Constant | ConstantIndex
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/// uint8 : Size in Bytes
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/// uint16 : Dwarf RegNum
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/// int32 : Offset
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/// }
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/// }
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///
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/// Location Encoding, Type, Value:
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/// 0x1, Register, Reg (value in register)
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/// 0x2, Direct, Reg + Offset (frame index)
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/// 0x3, Indirect, [Reg + Offset] (spilled value)
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/// 0x4, Constant, Offset (small constant)
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/// 0x5, ConstIndex, Constants[Offset] (large constant)
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///
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void StackMaps::serializeToStackMapSection() {
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// Bail out if there's no stack map data.
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if (CSInfos.empty())
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return;
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MCContext &OutContext = AP.OutStreamer.getContext();
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const TargetRegisterInfo *TRI = AP.TM.getRegisterInfo();
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// Create the section.
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const MCSection *StackMapSection =
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OutContext.getObjectFileInfo()->getStackMapSection();
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AP.OutStreamer.SwitchSection(StackMapSection);
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// Emit a dummy symbol to force section inclusion.
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AP.OutStreamer.EmitLabel(
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OutContext.GetOrCreateSymbol(Twine("__LLVM_StackMaps")));
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// Serialize data.
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const char *WSMP = "Stack Maps: ";
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(void)WSMP;
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const MCRegisterInfo &MCRI = *OutContext.getRegisterInfo();
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DEBUG(dbgs() << "********** Stack Map Output **********\n");
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// Header.
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AP.OutStreamer.EmitIntValue(0, 4);
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// Num constants.
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AP.OutStreamer.EmitIntValue(ConstPool.getNumConstants(), 4);
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// Constant pool entries.
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for (unsigned i = 0; i < ConstPool.getNumConstants(); ++i)
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AP.OutStreamer.EmitIntValue(ConstPool.getConstant(i), 8);
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DEBUG(dbgs() << WSMP << "#callsites = " << CSInfos.size() << "\n");
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AP.OutStreamer.EmitIntValue(CSInfos.size(), 4);
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for (CallsiteInfoList::const_iterator CSII = CSInfos.begin(),
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CSIE = CSInfos.end();
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CSII != CSIE; ++CSII) {
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unsigned CallsiteID = CSII->ID;
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const LocationVec &CSLocs = CSII->Locations;
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DEBUG(dbgs() << WSMP << "callsite " << CallsiteID << "\n");
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// Verify stack map entry. It's better to communicate a problem to the
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// runtime than crash in case of in-process compilation. Currently, we do
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// simple overflow checks, but we may eventually communicate other
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// compilation errors this way.
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if (CSLocs.size() > UINT16_MAX) {
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AP.OutStreamer.EmitIntValue(UINT32_MAX, 4); // Invalid ID.
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AP.OutStreamer.EmitValue(CSII->CSOffsetExpr, 4);
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AP.OutStreamer.EmitIntValue(0, 2); // Reserved.
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AP.OutStreamer.EmitIntValue(0, 2); // 0 locations.
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continue;
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}
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AP.OutStreamer.EmitIntValue(CallsiteID, 4);
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AP.OutStreamer.EmitValue(CSII->CSOffsetExpr, 4);
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// Reserved for flags.
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AP.OutStreamer.EmitIntValue(0, 2);
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DEBUG(dbgs() << WSMP << " has " << CSLocs.size() << " locations\n");
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AP.OutStreamer.EmitIntValue(CSLocs.size(), 2);
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unsigned operIdx = 0;
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for (LocationVec::const_iterator LocI = CSLocs.begin(), LocE = CSLocs.end();
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LocI != LocE; ++LocI, ++operIdx) {
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const Location &Loc = *LocI;
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unsigned RegNo = 0;
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int Offset = Loc.Offset;
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if(Loc.Reg) {
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RegNo = MCRI.getDwarfRegNum(Loc.Reg, false);
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for (MCSuperRegIterator SR(Loc.Reg, TRI);
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SR.isValid() && (int)RegNo < 0; ++SR) {
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RegNo = TRI->getDwarfRegNum(*SR, false);
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}
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// If this is a register location, put the subregister byte offset in
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// the location offset.
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if (Loc.LocType == Location::Register) {
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assert(!Loc.Offset && "Register location should have zero offset");
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unsigned LLVMRegNo = MCRI.getLLVMRegNum(RegNo, false);
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unsigned SubRegIdx = MCRI.getSubRegIndex(LLVMRegNo, Loc.Reg);
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if (SubRegIdx)
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Offset = MCRI.getSubRegIdxOffset(SubRegIdx);
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}
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}
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else {
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assert(Loc.LocType != Location::Register &&
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"Missing location register");
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}
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DEBUG(
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dbgs() << WSMP << " Loc " << operIdx << ": ";
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switch (Loc.LocType) {
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case Location::Unprocessed:
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dbgs() << "<Unprocessed operand>";
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break;
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case Location::Register:
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dbgs() << "Register " << MCRI.getName(Loc.Reg);
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break;
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case Location::Direct:
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dbgs() << "Direct " << MCRI.getName(Loc.Reg);
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if (Loc.Offset)
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dbgs() << " + " << Loc.Offset;
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break;
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case Location::Indirect:
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dbgs() << "Indirect " << MCRI.getName(Loc.Reg)
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<< " + " << Loc.Offset;
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break;
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case Location::Constant:
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dbgs() << "Constant " << Loc.Offset;
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break;
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case Location::ConstantIndex:
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dbgs() << "Constant Index " << Loc.Offset;
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break;
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}
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dbgs() << " [encoding: .byte " << Loc.LocType
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<< ", .byte " << Loc.Size
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<< ", .short " << RegNo
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<< ", .int " << Offset << "]\n";
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);
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AP.OutStreamer.EmitIntValue(Loc.LocType, 1);
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AP.OutStreamer.EmitIntValue(Loc.Size, 1);
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AP.OutStreamer.EmitIntValue(RegNo, 2);
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AP.OutStreamer.EmitIntValue(Offset, 4);
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}
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}
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AP.OutStreamer.AddBlankLine();
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CSInfos.clear();
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}
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