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llvm/test/CodeGen/Mips/msa/i8.ll
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Daniel Sanders c385709d83 [mips][msa] Added support for matching bmnz, bmnzi, bmz, and bmzi from normal IR (i.e. not intrinsics) 
Also corrected the definition of the intrinsics for these instructions (the
result register is also the first operand), and added intrinsics for bsel and
bseli to clang (they already existed in the backend).

These four operations are mostly equivalent to bsel, and bseli (the difference
is which operand is tied to the result). As a result some of the tests changed
as described below.

bitwise.ll:
- bsel.v test adapted so that the mask is unknown at compile-time. This stops
  it emitting bmnzi.b instead of the intended bsel.v.
- The bseli.b test now tests the right thing. Namely the case when one of the
  values is an uimm8, rather than when the condition is a uimm8 (which is
  covered by bmnzi.b)

compare.ll:
- bsel.v tests now (correctly) emits bmnz.v instead of bsel.v because this
  is the same operation (see MSA.txt).

i8.ll
- CHECK-DAG-ized test.
- bmzi.b test now (correctly) emits equivalent bmnzi.b with swapped operands
  because this is the same operation (see MSA.txt).
- bseli.b still emits bseli.b though because the immediate makes it
  distinguishable from bmnzi.b.

vec.ll:
- CHECK-DAG-ized test.
- bmz.v tests now (correctly) emits bmnz.v with swapped operands (see
  MSA.txt).
- bsel.v tests now (correctly) emits bmnz.v with swapped operands (see
  MSA.txt).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193693 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-30 15:20:38 +00:00

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; Test the MSA intrinsics that are encoded with the I8 instruction format.
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_andi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_andi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
define void @llvm_mips_andi_b_test() nounwind {
entry:
%0 = load <16 x i8>* @llvm_mips_andi_b_ARG1
%1 = tail call <16 x i8> @llvm.mips.andi.b(<16 x i8> %0, i32 25)
store <16 x i8> %1, <16 x i8>* @llvm_mips_andi_b_RES
ret void
}
declare <16 x i8> @llvm.mips.andi.b(<16 x i8>, i32) nounwind
; CHECK: llvm_mips_andi_b_test:
; CHECK: ld.b
; CHECK: andi.b
; CHECK: st.b
; CHECK: .size llvm_mips_andi_b_test
@llvm_mips_bmnzi_b_ARG1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
@llvm_mips_bmnzi_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_bmnzi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
define void @llvm_mips_bmnzi_b_test() nounwind {
entry:
%0 = load <16 x i8>* @llvm_mips_bmnzi_b_ARG1
%1 = load <16 x i8>* @llvm_mips_bmnzi_b_ARG2
%2 = tail call <16 x i8> @llvm.mips.bmnzi.b(<16 x i8> %0, <16 x i8> %1, i32 25)
store <16 x i8> %2, <16 x i8>* @llvm_mips_bmnzi_b_RES
ret void
}
declare <16 x i8> @llvm.mips.bmnzi.b(<16 x i8>, <16 x i8>, i32) nounwind
; CHECK: llvm_mips_bmnzi_b_test:
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_bmnzi_b_ARG1)(
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_bmnzi_b_ARG2)(
; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]])
; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]])
; CHECK-DAG: bmnzi.b [[R3]], [[R4]], 25
; CHECK-DAG: st.b [[R3]], 0(
; CHECK: .size llvm_mips_bmnzi_b_test
@llvm_mips_bmzi_b_ARG1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
@llvm_mips_bmzi_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_bmzi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
define void @llvm_mips_bmzi_b_test() nounwind {
entry:
%0 = load <16 x i8>* @llvm_mips_bmzi_b_ARG1
%1 = load <16 x i8>* @llvm_mips_bmzi_b_ARG2
%2 = tail call <16 x i8> @llvm.mips.bmzi.b(<16 x i8> %0, <16 x i8> %1, i32 25)
store <16 x i8> %2, <16 x i8>* @llvm_mips_bmzi_b_RES
ret void
}
declare <16 x i8> @llvm.mips.bmzi.b(<16 x i8>, <16 x i8>, i32) nounwind
; CHECK: llvm_mips_bmzi_b_test:
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_bmzi_b_ARG1)(
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_bmzi_b_ARG2)(
; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]])
; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]])
; bmnzi.b is the same as bmzi.b with ws and wd_in swapped
; CHECK-DAG: bmnzi.b [[R4]], [[R3]], 25
; CHECK-DAG: st.b [[R4]], 0(
; CHECK: .size llvm_mips_bmzi_b_test
@llvm_mips_bseli_b_ARG1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
@llvm_mips_bseli_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_bseli_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
define void @llvm_mips_bseli_b_test() nounwind {
entry:
%0 = load <16 x i8>* @llvm_mips_bseli_b_ARG1
%1 = load <16 x i8>* @llvm_mips_bseli_b_ARG2
%2 = tail call <16 x i8> @llvm.mips.bseli.b(<16 x i8> %0, <16 x i8> %1, i32 25)
store <16 x i8> %2, <16 x i8>* @llvm_mips_bseli_b_RES
ret void
}
declare <16 x i8> @llvm.mips.bseli.b(<16 x i8>, <16 x i8>, i32) nounwind
; CHECK: llvm_mips_bseli_b_test:
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_bseli_b_ARG1)(
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_bseli_b_ARG2)(
; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]])
; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]])
; CHECK-DAG: bseli.b [[R3]], [[R4]], 25
; CHECK-DAG: st.b [[R3]], 0(
; CHECK: .size llvm_mips_bseli_b_test
@llvm_mips_nori_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_nori_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
define void @llvm_mips_nori_b_test() nounwind {
entry:
%0 = load <16 x i8>* @llvm_mips_nori_b_ARG1
%1 = tail call <16 x i8> @llvm.mips.nori.b(<16 x i8> %0, i32 25)
store <16 x i8> %1, <16 x i8>* @llvm_mips_nori_b_RES
ret void
}
declare <16 x i8> @llvm.mips.nori.b(<16 x i8>, i32) nounwind
; CHECK: llvm_mips_nori_b_test:
; CHECK: ld.b
; CHECK: nori.b
; CHECK: st.b
; CHECK: .size llvm_mips_nori_b_test
;
@llvm_mips_ori_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_ori_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
define void @llvm_mips_ori_b_test() nounwind {
entry:
%0 = load <16 x i8>* @llvm_mips_ori_b_ARG1
%1 = tail call <16 x i8> @llvm.mips.ori.b(<16 x i8> %0, i32 25)
store <16 x i8> %1, <16 x i8>* @llvm_mips_ori_b_RES
ret void
}
declare <16 x i8> @llvm.mips.ori.b(<16 x i8>, i32) nounwind
; CHECK: llvm_mips_ori_b_test:
; CHECK: ld.b
; CHECK: ori.b
; CHECK: st.b
; CHECK: .size llvm_mips_ori_b_test
;
@llvm_mips_shf_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_shf_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
define void @llvm_mips_shf_b_test() nounwind {
entry:
%0 = load <16 x i8>* @llvm_mips_shf_b_ARG1
%1 = tail call <16 x i8> @llvm.mips.shf.b(<16 x i8> %0, i32 25)
store <16 x i8> %1, <16 x i8>* @llvm_mips_shf_b_RES
ret void
}
declare <16 x i8> @llvm.mips.shf.b(<16 x i8>, i32) nounwind
; CHECK: llvm_mips_shf_b_test:
; CHECK: ld.b
; CHECK: shf.b
; CHECK: st.b
; CHECK: .size llvm_mips_shf_b_test
;
@llvm_mips_shf_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
@llvm_mips_shf_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
define void @llvm_mips_shf_h_test() nounwind {
entry:
%0 = load <8 x i16>* @llvm_mips_shf_h_ARG1
%1 = tail call <8 x i16> @llvm.mips.shf.h(<8 x i16> %0, i32 25)
store <8 x i16> %1, <8 x i16>* @llvm_mips_shf_h_RES
ret void
}
declare <8 x i16> @llvm.mips.shf.h(<8 x i16>, i32) nounwind
; CHECK: llvm_mips_shf_h_test:
; CHECK: ld.h
; CHECK: shf.h
; CHECK: st.h
; CHECK: .size llvm_mips_shf_h_test
;
@llvm_mips_shf_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
@llvm_mips_shf_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
define void @llvm_mips_shf_w_test() nounwind {
entry:
%0 = load <4 x i32>* @llvm_mips_shf_w_ARG1
%1 = tail call <4 x i32> @llvm.mips.shf.w(<4 x i32> %0, i32 25)
store <4 x i32> %1, <4 x i32>* @llvm_mips_shf_w_RES
ret void
}
declare <4 x i32> @llvm.mips.shf.w(<4 x i32>, i32) nounwind
; CHECK: llvm_mips_shf_w_test:
; CHECK: ld.w
; CHECK: shf.w
; CHECK: st.w
; CHECK: .size llvm_mips_shf_w_test
;
@llvm_mips_xori_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_xori_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
define void @llvm_mips_xori_b_test() nounwind {
entry:
%0 = load <16 x i8>* @llvm_mips_xori_b_ARG1
%1 = tail call <16 x i8> @llvm.mips.xori.b(<16 x i8> %0, i32 25)
store <16 x i8> %1, <16 x i8>* @llvm_mips_xori_b_RES
ret void
}
declare <16 x i8> @llvm.mips.xori.b(<16 x i8>, i32) nounwind
; CHECK: llvm_mips_xori_b_test:
; CHECK: ld.b
; CHECK: xori.b
; CHECK: st.b
; CHECK: .size llvm_mips_xori_b_test
;
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