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llvm/test/CodeGen
Simon Pilgrim d4f7cbfea6 [X86][AVX] Start shuffle combining from ZERO_EXTEND_VECTOR_INREG (PR40685)
Just enable this for AVX for now as SSE41 introduces extra register moves for the PMOVZX(PSHUFD(V)) -> UNPCKH(V,0) pattern (but otherwise helps reduce port5 usage on Intel targets).

Only AVX support is required for PR40685 as the issue is due to 8i8->8i32 zext shuffle leftovers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356858 91177308-0d34-0410-b5e6-96231b3b80d8
2019-03-24 16:30:35 +00:00
..
2019-03-21 20:56:05 +00:00
2019-03-02 08:03:59 +00:00