mirror of
https://github.com/RPCS3/llvm.git
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533297b58d
bunch of associated comments, because it doesn't have anything to do with DAGs or scheduling. This is another step in decoupling MachineInstr emitting from scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
341 lines
16 KiB
TableGen
341 lines
16 KiB
TableGen
//===- SystemZInstrFP.td - SystemZ FP Instruction defs --------*- tblgen-*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the SystemZ (binary) floating point instructions in
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// TableGen format.
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//
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//===----------------------------------------------------------------------===//
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// FIXME: multiclassify!
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//===----------------------------------------------------------------------===//
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// FP Pattern fragments
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def fpimm0 : PatLeaf<(fpimm), [{
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return N->isExactlyValue(+0.0);
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}]>;
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def fpimmneg0 : PatLeaf<(fpimm), [{
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return N->isExactlyValue(-0.0);
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}]>;
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let Uses = [PSW], usesCustomInserter = 1 in {
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def SelectF32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, i8imm:$cc),
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"# SelectF32 PSEUDO",
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[(set FP32:$dst,
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(SystemZselect FP32:$src1, FP32:$src2, imm:$cc, PSW))]>;
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def SelectF64 : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, i8imm:$cc),
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"# SelectF64 PSEUDO",
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[(set FP64:$dst,
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(SystemZselect FP64:$src1, FP64:$src2, imm:$cc, PSW))]>;
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}
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//===----------------------------------------------------------------------===//
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// Move Instructions
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// Floating point constant loads.
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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def LD_Fp032 : Pseudo<(outs FP32:$dst), (ins),
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"lzer\t{$dst}",
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[(set FP32:$dst, fpimm0)]>;
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def LD_Fp064 : Pseudo<(outs FP64:$dst), (ins),
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"lzdr\t{$dst}",
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[(set FP64:$dst, fpimm0)]>;
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}
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let neverHasSideEffects = 1 in {
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def FMOV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
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"ler\t{$dst, $src}",
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[]>;
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def FMOV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
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"ldr\t{$dst, $src}",
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[]>;
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}
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let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
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def FMOV32rm : Pseudo<(outs FP32:$dst), (ins rriaddr12:$src),
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"le\t{$dst, $src}",
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[(set FP32:$dst, (load rriaddr12:$src))]>;
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def FMOV32rmy : Pseudo<(outs FP32:$dst), (ins rriaddr:$src),
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"ley\t{$dst, $src}",
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[(set FP32:$dst, (load rriaddr:$src))]>;
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def FMOV64rm : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src),
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"ld\t{$dst, $src}",
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[(set FP64:$dst, (load rriaddr12:$src))]>;
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def FMOV64rmy : Pseudo<(outs FP64:$dst), (ins rriaddr:$src),
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"ldy\t{$dst, $src}",
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[(set FP64:$dst, (load rriaddr:$src))]>;
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}
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def FMOV32mr : Pseudo<(outs), (ins rriaddr12:$dst, FP32:$src),
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"ste\t{$src, $dst}",
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[(store FP32:$src, rriaddr12:$dst)]>;
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def FMOV32mry : Pseudo<(outs), (ins rriaddr:$dst, FP32:$src),
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"stey\t{$src, $dst}",
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[(store FP32:$src, rriaddr:$dst)]>;
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def FMOV64mr : Pseudo<(outs), (ins rriaddr12:$dst, FP64:$src),
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"std\t{$src, $dst}",
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[(store FP64:$src, rriaddr12:$dst)]>;
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def FMOV64mry : Pseudo<(outs), (ins rriaddr:$dst, FP64:$src),
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"stdy\t{$src, $dst}",
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[(store FP64:$src, rriaddr:$dst)]>;
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def FCOPYSIGN32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
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"cpsdr\t{$dst, $src2, $src1}",
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[(set FP32:$dst, (fcopysign FP32:$src1, FP32:$src2))]>;
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def FCOPYSIGN64 : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
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"cpsdr\t{$dst, $src2, $src1}",
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[(set FP64:$dst, (fcopysign FP64:$src1, FP64:$src2))]>;
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//===----------------------------------------------------------------------===//
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// Arithmetic Instructions
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let Defs = [PSW] in {
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def FNEG32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
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"lcebr\t{$dst, $src}",
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[(set FP32:$dst, (fneg FP32:$src)),
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(implicit PSW)]>;
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def FNEG64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
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"lcdbr\t{$dst, $src}",
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[(set FP64:$dst, (fneg FP64:$src)),
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(implicit PSW)]>;
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def FABS32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
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"lpebr\t{$dst, $src}",
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[(set FP32:$dst, (fabs FP32:$src)),
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(implicit PSW)]>;
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def FABS64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
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"lpdbr\t{$dst, $src}",
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[(set FP64:$dst, (fabs FP64:$src)),
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(implicit PSW)]>;
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def FNABS32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
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"lnebr\t{$dst, $src}",
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[(set FP32:$dst, (fneg(fabs FP32:$src))),
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(implicit PSW)]>;
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def FNABS64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
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"lndbr\t{$dst, $src}",
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[(set FP64:$dst, (fneg(fabs FP64:$src))),
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(implicit PSW)]>;
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}
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let isTwoAddress = 1 in {
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let Defs = [PSW] in {
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let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
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def FADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
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"aebr\t{$dst, $src2}",
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[(set FP32:$dst, (fadd FP32:$src1, FP32:$src2)),
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(implicit PSW)]>;
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def FADD64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
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"adbr\t{$dst, $src2}",
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[(set FP64:$dst, (fadd FP64:$src1, FP64:$src2)),
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(implicit PSW)]>;
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}
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def FADD32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2),
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"aeb\t{$dst, $src2}",
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[(set FP32:$dst, (fadd FP32:$src1, (load rriaddr12:$src2))),
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(implicit PSW)]>;
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def FADD64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2),
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"adb\t{$dst, $src2}",
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[(set FP64:$dst, (fadd FP64:$src1, (load rriaddr12:$src2))),
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(implicit PSW)]>;
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def FSUB32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
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"sebr\t{$dst, $src2}",
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[(set FP32:$dst, (fsub FP32:$src1, FP32:$src2)),
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(implicit PSW)]>;
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def FSUB64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
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"sdbr\t{$dst, $src2}",
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[(set FP64:$dst, (fsub FP64:$src1, FP64:$src2)),
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(implicit PSW)]>;
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def FSUB32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2),
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"seb\t{$dst, $src2}",
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[(set FP32:$dst, (fsub FP32:$src1, (load rriaddr12:$src2))),
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(implicit PSW)]>;
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def FSUB64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2),
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"sdb\t{$dst, $src2}",
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[(set FP64:$dst, (fsub FP64:$src1, (load rriaddr12:$src2))),
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(implicit PSW)]>;
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} // Defs = [PSW]
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let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y
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def FMUL32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
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"meebr\t{$dst, $src2}",
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[(set FP32:$dst, (fmul FP32:$src1, FP32:$src2))]>;
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def FMUL64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
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"mdbr\t{$dst, $src2}",
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[(set FP64:$dst, (fmul FP64:$src1, FP64:$src2))]>;
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}
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def FMUL32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2),
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"meeb\t{$dst, $src2}",
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[(set FP32:$dst, (fmul FP32:$src1, (load rriaddr12:$src2)))]>;
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def FMUL64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2),
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"mdb\t{$dst, $src2}",
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[(set FP64:$dst, (fmul FP64:$src1, (load rriaddr12:$src2)))]>;
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def FMADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, FP32:$src3),
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"maebr\t{$dst, $src3, $src2}",
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[(set FP32:$dst, (fadd (fmul FP32:$src2, FP32:$src3),
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FP32:$src1))]>;
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def FMADD32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2, FP32:$src3),
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"maeb\t{$dst, $src3, $src2}",
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[(set FP32:$dst, (fadd (fmul (load rriaddr12:$src2),
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FP32:$src3),
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FP32:$src1))]>;
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def FMADD64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, FP64:$src3),
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"madbr\t{$dst, $src3, $src2}",
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[(set FP64:$dst, (fadd (fmul FP64:$src2, FP64:$src3),
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FP64:$src1))]>;
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def FMADD64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2, FP64:$src3),
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"madb\t{$dst, $src3, $src2}",
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[(set FP64:$dst, (fadd (fmul (load rriaddr12:$src2),
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FP64:$src3),
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FP64:$src1))]>;
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def FMSUB32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, FP32:$src3),
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"msebr\t{$dst, $src3, $src2}",
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[(set FP32:$dst, (fsub (fmul FP32:$src2, FP32:$src3),
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FP32:$src1))]>;
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def FMSUB32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2, FP32:$src3),
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"mseb\t{$dst, $src3, $src2}",
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[(set FP32:$dst, (fsub (fmul (load rriaddr12:$src2),
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FP32:$src3),
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FP32:$src1))]>;
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def FMSUB64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, FP64:$src3),
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"msdbr\t{$dst, $src3, $src2}",
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[(set FP64:$dst, (fsub (fmul FP64:$src2, FP64:$src3),
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FP64:$src1))]>;
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def FMSUB64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2, FP64:$src3),
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"msdb\t{$dst, $src3, $src2}",
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[(set FP64:$dst, (fsub (fmul (load rriaddr12:$src2),
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FP64:$src3),
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FP64:$src1))]>;
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def FDIV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
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"debr\t{$dst, $src2}",
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[(set FP32:$dst, (fdiv FP32:$src1, FP32:$src2))]>;
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def FDIV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
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"ddbr\t{$dst, $src2}",
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[(set FP64:$dst, (fdiv FP64:$src1, FP64:$src2))]>;
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def FDIV32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr12:$src2),
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"deb\t{$dst, $src2}",
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[(set FP32:$dst, (fdiv FP32:$src1, (load rriaddr12:$src2)))]>;
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def FDIV64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr12:$src2),
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"ddb\t{$dst, $src2}",
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[(set FP64:$dst, (fdiv FP64:$src1, (load rriaddr12:$src2)))]>;
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} // isTwoAddress = 1
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def FSQRT32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
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"sqebr\t{$dst, $src}",
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[(set FP32:$dst, (fsqrt FP32:$src))]>;
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def FSQRT64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
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"sqdbr\t{$dst, $src}",
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[(set FP64:$dst, (fsqrt FP64:$src))]>;
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def FSQRT32rm : Pseudo<(outs FP32:$dst), (ins rriaddr12:$src),
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"sqeb\t{$dst, $src}",
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[(set FP32:$dst, (fsqrt (load rriaddr12:$src)))]>;
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def FSQRT64rm : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src),
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"sqdb\t{$dst, $src}",
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[(set FP64:$dst, (fsqrt (load rriaddr12:$src)))]>;
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def FROUND64r32 : Pseudo<(outs FP32:$dst), (ins FP64:$src),
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"ledbr\t{$dst, $src}",
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[(set FP32:$dst, (fround FP64:$src))]>;
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def FEXT32r64 : Pseudo<(outs FP64:$dst), (ins FP32:$src),
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"ldebr\t{$dst, $src}",
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[(set FP64:$dst, (fextend FP32:$src))]>;
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def FEXT32m64 : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src),
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"ldeb\t{$dst, $src}",
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[(set FP64:$dst, (fextend (load rriaddr12:$src)))]>;
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let Defs = [PSW] in {
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def FCONVFP32 : Pseudo<(outs FP32:$dst), (ins GR32:$src),
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"cefbr\t{$dst, $src}",
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[(set FP32:$dst, (sint_to_fp GR32:$src)),
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(implicit PSW)]>;
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def FCONVFP32r64: Pseudo<(outs FP32:$dst), (ins GR64:$src),
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"cegbr\t{$dst, $src}",
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[(set FP32:$dst, (sint_to_fp GR64:$src)),
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(implicit PSW)]>;
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def FCONVFP64r32: Pseudo<(outs FP64:$dst), (ins GR32:$src),
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"cdfbr\t{$dst, $src}",
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[(set FP64:$dst, (sint_to_fp GR32:$src)),
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(implicit PSW)]>;
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def FCONVFP64 : Pseudo<(outs FP64:$dst), (ins GR64:$src),
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"cdgbr\t{$dst, $src}",
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[(set FP64:$dst, (sint_to_fp GR64:$src)),
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(implicit PSW)]>;
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def FCONVGR32 : Pseudo<(outs GR32:$dst), (ins FP32:$src),
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"cfebr\t{$dst, 5, $src}",
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[(set GR32:$dst, (fp_to_sint FP32:$src)),
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(implicit PSW)]>;
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def FCONVGR32r64: Pseudo<(outs GR32:$dst), (ins FP64:$src),
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"cfdbr\t{$dst, 5, $src}",
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[(set GR32:$dst, (fp_to_sint FP64:$src)),
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(implicit PSW)]>;
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def FCONVGR64r32: Pseudo<(outs GR64:$dst), (ins FP32:$src),
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"cgebr\t{$dst, 5, $src}",
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[(set GR64:$dst, (fp_to_sint FP32:$src)),
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(implicit PSW)]>;
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def FCONVGR64 : Pseudo<(outs GR64:$dst), (ins FP64:$src),
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"cgdbr\t{$dst, 5, $src}",
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[(set GR64:$dst, (fp_to_sint FP64:$src)),
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(implicit PSW)]>;
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} // Defs = [PSW]
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def FBCONVG64 : Pseudo<(outs GR64:$dst), (ins FP64:$src),
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"lgdr\t{$dst, $src}",
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[(set GR64:$dst, (bitconvert FP64:$src))]>;
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def FBCONVF64 : Pseudo<(outs FP64:$dst), (ins GR64:$src),
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"ldgr\t{$dst, $src}",
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[(set FP64:$dst, (bitconvert GR64:$src))]>;
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//===----------------------------------------------------------------------===//
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// Test instructions (like AND but do not produce any result)
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// Integer comparisons
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let Defs = [PSW] in {
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def FCMP32rr : Pseudo<(outs), (ins FP32:$src1, FP32:$src2),
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"cebr\t$src1, $src2",
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[(SystemZcmp FP32:$src1, FP32:$src2), (implicit PSW)]>;
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def FCMP64rr : Pseudo<(outs), (ins FP64:$src1, FP64:$src2),
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"cdbr\t$src1, $src2",
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[(SystemZcmp FP64:$src1, FP64:$src2), (implicit PSW)]>;
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def FCMP32rm : Pseudo<(outs), (ins FP32:$src1, rriaddr12:$src2),
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"ceb\t$src1, $src2",
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[(SystemZcmp FP32:$src1, (load rriaddr12:$src2)),
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(implicit PSW)]>;
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def FCMP64rm : Pseudo<(outs), (ins FP64:$src1, rriaddr12:$src2),
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"cdb\t$src1, $src2",
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[(SystemZcmp FP64:$src1, (load rriaddr12:$src2)),
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(implicit PSW)]>;
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} // Defs = [PSW]
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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//===----------------------------------------------------------------------===//
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// Floating point constant -0.0
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def : Pat<(f32 fpimmneg0), (FNEG32rr (LD_Fp032))>;
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def : Pat<(f64 fpimmneg0), (FNEG64rr (LD_Fp064))>;
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