mirror of
https://github.com/RPCS3/llvm.git
synced 2026-07-24 20:25:32 -04:00
Matt Arsenault
d5a79b9727
This is incomplete, and ideally these would all be removed, but it's better to localize them to the subtarget first with comments about what they're for. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363902 91177308-0d34-0410-b5e6-96231b3b80d8
1030 lines
34 KiB
C++
1030 lines
34 KiB
C++
//===- AMDGPULegalizerInfo.cpp -----------------------------------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the Machinelegalizer class for
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/// AMDGPU.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPULegalizerInfo.h"
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#include "AMDGPUTargetMachine.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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using namespace LegalizeActions;
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using namespace LegalizeMutations;
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using namespace LegalityPredicates;
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static LegalityPredicate isMultiple32(unsigned TypeIdx,
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unsigned MaxSize = 512) {
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return [=](const LegalityQuery &Query) {
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const LLT Ty = Query.Types[TypeIdx];
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const LLT EltTy = Ty.getScalarType();
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return Ty.getSizeInBits() <= MaxSize && EltTy.getSizeInBits() % 32 == 0;
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};
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}
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static LegalityPredicate isSmallOddVector(unsigned TypeIdx) {
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return [=](const LegalityQuery &Query) {
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const LLT Ty = Query.Types[TypeIdx];
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return Ty.isVector() &&
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Ty.getNumElements() % 2 != 0 &&
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Ty.getElementType().getSizeInBits() < 32;
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};
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}
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static LegalizeMutation oneMoreElement(unsigned TypeIdx) {
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return [=](const LegalityQuery &Query) {
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const LLT Ty = Query.Types[TypeIdx];
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const LLT EltTy = Ty.getElementType();
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return std::make_pair(TypeIdx, LLT::vector(Ty.getNumElements() + 1, EltTy));
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};
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}
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static LegalizeMutation fewerEltsToSize64Vector(unsigned TypeIdx) {
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return [=](const LegalityQuery &Query) {
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const LLT Ty = Query.Types[TypeIdx];
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const LLT EltTy = Ty.getElementType();
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unsigned Size = Ty.getSizeInBits();
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unsigned Pieces = (Size + 63) / 64;
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unsigned NewNumElts = (Ty.getNumElements() + 1) / Pieces;
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return std::make_pair(TypeIdx, LLT::scalarOrVector(NewNumElts, EltTy));
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};
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}
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static LegalityPredicate vectorWiderThan(unsigned TypeIdx, unsigned Size) {
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return [=](const LegalityQuery &Query) {
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const LLT QueryTy = Query.Types[TypeIdx];
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return QueryTy.isVector() && QueryTy.getSizeInBits() > Size;
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};
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}
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static LegalityPredicate numElementsNotEven(unsigned TypeIdx) {
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return [=](const LegalityQuery &Query) {
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const LLT QueryTy = Query.Types[TypeIdx];
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return QueryTy.isVector() && QueryTy.getNumElements() % 2 != 0;
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};
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}
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AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
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const GCNTargetMachine &TM) {
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using namespace TargetOpcode;
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auto GetAddrSpacePtr = [&TM](unsigned AS) {
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return LLT::pointer(AS, TM.getPointerSizeInBits(AS));
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};
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const LLT S1 = LLT::scalar(1);
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const LLT S8 = LLT::scalar(8);
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const LLT S16 = LLT::scalar(16);
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const LLT S32 = LLT::scalar(32);
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const LLT S64 = LLT::scalar(64);
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const LLT S128 = LLT::scalar(128);
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const LLT S256 = LLT::scalar(256);
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const LLT S512 = LLT::scalar(512);
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const LLT V2S16 = LLT::vector(2, 16);
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const LLT V4S16 = LLT::vector(4, 16);
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const LLT V8S16 = LLT::vector(8, 16);
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const LLT V2S32 = LLT::vector(2, 32);
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const LLT V3S32 = LLT::vector(3, 32);
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const LLT V4S32 = LLT::vector(4, 32);
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const LLT V5S32 = LLT::vector(5, 32);
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const LLT V6S32 = LLT::vector(6, 32);
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const LLT V7S32 = LLT::vector(7, 32);
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const LLT V8S32 = LLT::vector(8, 32);
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const LLT V9S32 = LLT::vector(9, 32);
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const LLT V10S32 = LLT::vector(10, 32);
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const LLT V11S32 = LLT::vector(11, 32);
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const LLT V12S32 = LLT::vector(12, 32);
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const LLT V13S32 = LLT::vector(13, 32);
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const LLT V14S32 = LLT::vector(14, 32);
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const LLT V15S32 = LLT::vector(15, 32);
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const LLT V16S32 = LLT::vector(16, 32);
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const LLT V2S64 = LLT::vector(2, 64);
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const LLT V3S64 = LLT::vector(3, 64);
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const LLT V4S64 = LLT::vector(4, 64);
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const LLT V5S64 = LLT::vector(5, 64);
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const LLT V6S64 = LLT::vector(6, 64);
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const LLT V7S64 = LLT::vector(7, 64);
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const LLT V8S64 = LLT::vector(8, 64);
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std::initializer_list<LLT> AllS32Vectors =
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{V2S32, V3S32, V4S32, V5S32, V6S32, V7S32, V8S32,
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V9S32, V10S32, V11S32, V12S32, V13S32, V14S32, V15S32, V16S32};
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std::initializer_list<LLT> AllS64Vectors =
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{V2S64, V3S64, V4S64, V5S64, V6S64, V7S64, V8S64};
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const LLT GlobalPtr = GetAddrSpacePtr(AMDGPUAS::GLOBAL_ADDRESS);
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const LLT ConstantPtr = GetAddrSpacePtr(AMDGPUAS::CONSTANT_ADDRESS);
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const LLT LocalPtr = GetAddrSpacePtr(AMDGPUAS::LOCAL_ADDRESS);
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const LLT FlatPtr = GetAddrSpacePtr(AMDGPUAS::FLAT_ADDRESS);
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const LLT PrivatePtr = GetAddrSpacePtr(AMDGPUAS::PRIVATE_ADDRESS);
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const LLT CodePtr = FlatPtr;
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const std::initializer_list<LLT> AddrSpaces64 = {
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GlobalPtr, ConstantPtr, FlatPtr
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};
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const std::initializer_list<LLT> AddrSpaces32 = {
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LocalPtr, PrivatePtr
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};
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setAction({G_BRCOND, S1}, Legal);
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// TODO: All multiples of 32, vectors of pointers, all v2s16 pairs, more
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// elements for v3s16
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getActionDefinitionsBuilder(G_PHI)
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.legalFor({S32, S64, V2S16, V4S16, S1, S128, S256})
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.legalFor(AllS32Vectors)
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.legalFor(AllS64Vectors)
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.legalFor(AddrSpaces64)
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.legalFor(AddrSpaces32)
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.clampScalar(0, S32, S256)
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.widenScalarToNextPow2(0, 32)
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.clampMaxNumElements(0, S32, 16)
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.moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
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.legalIf(isPointer(0));
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getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL, G_UMULH, G_SMULH})
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.legalFor({S32})
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.clampScalar(0, S32, S32)
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.scalarize(0);
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// Report legal for any types we can handle anywhere. For the cases only legal
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// on the SALU, RegBankSelect will be able to re-legalize.
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getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
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.legalFor({S32, S1, S64, V2S32, V2S16, V4S16})
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.clampScalar(0, S32, S64)
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.moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
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.fewerElementsIf(vectorWiderThan(0, 32), fewerEltsToSize64Vector(0))
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.widenScalarToNextPow2(0)
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.scalarize(0);
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getActionDefinitionsBuilder({G_UADDO, G_SADDO, G_USUBO, G_SSUBO,
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G_UADDE, G_SADDE, G_USUBE, G_SSUBE})
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.legalFor({{S32, S1}})
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.clampScalar(0, S32, S32);
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getActionDefinitionsBuilder(G_BITCAST)
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.legalForCartesianProduct({S32, V2S16})
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.legalForCartesianProduct({S64, V2S32, V4S16})
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.legalForCartesianProduct({V2S64, V4S32})
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// Don't worry about the size constraint.
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.legalIf(all(isPointer(0), isPointer(1)));
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if (ST.has16BitInsts()) {
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getActionDefinitionsBuilder(G_FCONSTANT)
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.legalFor({S32, S64, S16})
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.clampScalar(0, S16, S64);
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} else {
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getActionDefinitionsBuilder(G_FCONSTANT)
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.legalFor({S32, S64})
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.clampScalar(0, S32, S64);
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}
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getActionDefinitionsBuilder(G_IMPLICIT_DEF)
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.legalFor({S1, S32, S64, V2S32, V4S32, V2S16, V4S16, GlobalPtr,
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ConstantPtr, LocalPtr, FlatPtr, PrivatePtr})
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.moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
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.clampScalarOrElt(0, S32, S512)
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.legalIf(isMultiple32(0))
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.widenScalarToNextPow2(0, 32)
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.clampMaxNumElements(0, S32, 16);
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// FIXME: i1 operands to intrinsics should always be legal, but other i1
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// values may not be legal. We need to figure out how to distinguish
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// between these two scenarios.
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getActionDefinitionsBuilder(G_CONSTANT)
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.legalFor({S1, S32, S64, GlobalPtr,
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LocalPtr, ConstantPtr, PrivatePtr, FlatPtr })
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.clampScalar(0, S32, S64)
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.widenScalarToNextPow2(0)
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.legalIf(isPointer(0));
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setAction({G_FRAME_INDEX, PrivatePtr}, Legal);
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auto &FPOpActions = getActionDefinitionsBuilder(
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{ G_FADD, G_FMUL, G_FNEG, G_FABS, G_FMA, G_FCANONICALIZE})
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.legalFor({S32, S64});
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if (ST.has16BitInsts()) {
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if (ST.hasVOP3PInsts())
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FPOpActions.legalFor({S16, V2S16});
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else
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FPOpActions.legalFor({S16});
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}
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if (ST.hasVOP3PInsts())
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FPOpActions.clampMaxNumElements(0, S16, 2);
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FPOpActions
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.scalarize(0)
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.clampScalar(0, ST.has16BitInsts() ? S16 : S32, S64);
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if (ST.has16BitInsts()) {
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getActionDefinitionsBuilder(G_FSQRT)
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.legalFor({S32, S64, S16})
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.scalarize(0)
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.clampScalar(0, S16, S64);
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} else {
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getActionDefinitionsBuilder(G_FSQRT)
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.legalFor({S32, S64})
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.scalarize(0)
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.clampScalar(0, S32, S64);
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}
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getActionDefinitionsBuilder(G_FPTRUNC)
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.legalFor({{S32, S64}, {S16, S32}})
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.scalarize(0);
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getActionDefinitionsBuilder(G_FPEXT)
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.legalFor({{S64, S32}, {S32, S16}})
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.lowerFor({{S64, S16}}) // FIXME: Implement
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.scalarize(0);
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getActionDefinitionsBuilder(G_FCOPYSIGN)
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.legalForCartesianProduct({S16, S32, S64}, {S16, S32, S64})
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.scalarize(0);
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getActionDefinitionsBuilder(G_FSUB)
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// Use actual fsub instruction
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.legalFor({S32})
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// Must use fadd + fneg
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.lowerFor({S64, S16, V2S16})
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.scalarize(0)
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.clampScalar(0, S32, S64);
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getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
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.legalFor({{S64, S32}, {S32, S16}, {S64, S16},
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{S32, S1}, {S64, S1}, {S16, S1},
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// FIXME: Hack
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{S64, LLT::scalar(33)},
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{S32, S8}, {S128, S32}, {S128, S64}, {S32, LLT::scalar(24)}})
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.scalarize(0);
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getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
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.legalFor({{S32, S32}, {S64, S32}})
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.lowerFor({{S32, S64}})
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.customFor({{S64, S64}})
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.scalarize(0);
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getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
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.legalFor({{S32, S32}, {S32, S64}})
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.scalarize(0);
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getActionDefinitionsBuilder(G_INTRINSIC_ROUND)
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.legalFor({S32, S64})
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.scalarize(0);
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if (ST.getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) {
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getActionDefinitionsBuilder({G_INTRINSIC_TRUNC, G_FCEIL, G_FRINT})
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.legalFor({S32, S64})
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.clampScalar(0, S32, S64)
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.scalarize(0);
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} else {
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getActionDefinitionsBuilder({G_INTRINSIC_TRUNC, G_FCEIL, G_FRINT})
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.legalFor({S32})
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.customFor({S64})
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.clampScalar(0, S32, S64)
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.scalarize(0);
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}
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getActionDefinitionsBuilder(G_GEP)
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.legalForCartesianProduct(AddrSpaces64, {S64})
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.legalForCartesianProduct(AddrSpaces32, {S32})
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.scalarize(0);
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setAction({G_BLOCK_ADDR, CodePtr}, Legal);
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getActionDefinitionsBuilder(G_ICMP)
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.legalForCartesianProduct(
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{S1}, {S32, S64, GlobalPtr, LocalPtr, ConstantPtr, PrivatePtr, FlatPtr})
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.legalFor({{S1, S32}, {S1, S64}})
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.widenScalarToNextPow2(1)
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.clampScalar(1, S32, S64)
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.scalarize(0)
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.legalIf(all(typeIs(0, S1), isPointer(1)));
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getActionDefinitionsBuilder(G_FCMP)
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.legalFor({{S1, S32}, {S1, S64}})
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.widenScalarToNextPow2(1)
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.clampScalar(1, S32, S64)
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.scalarize(0);
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// FIXME: fexp, flog2, flog10 needs to be custom lowered.
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getActionDefinitionsBuilder({G_FPOW, G_FEXP, G_FEXP2,
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G_FLOG, G_FLOG2, G_FLOG10})
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.legalFor({S32})
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.scalarize(0);
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// The 64-bit versions produce 32-bit results, but only on the SALU.
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getActionDefinitionsBuilder({G_CTLZ, G_CTLZ_ZERO_UNDEF,
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G_CTTZ, G_CTTZ_ZERO_UNDEF,
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G_CTPOP})
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.legalFor({{S32, S32}, {S32, S64}})
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.clampScalar(0, S32, S32)
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.clampScalar(1, S32, S64)
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.scalarize(0)
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.widenScalarToNextPow2(0, 32)
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.widenScalarToNextPow2(1, 32);
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// TODO: Expand for > s32
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getActionDefinitionsBuilder(G_BSWAP)
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.legalFor({S32})
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.clampScalar(0, S32, S32)
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.scalarize(0);
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if (ST.has16BitInsts()) {
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if (ST.hasVOP3PInsts()) {
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getActionDefinitionsBuilder({G_SMIN, G_SMAX, G_UMIN, G_UMAX})
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.legalFor({S32, S16, V2S16})
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.moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
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.clampMaxNumElements(0, S16, 2)
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.clampScalar(0, S16, S32)
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.widenScalarToNextPow2(0)
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.scalarize(0);
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} else {
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getActionDefinitionsBuilder({G_SMIN, G_SMAX, G_UMIN, G_UMAX})
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.legalFor({S32, S16})
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.widenScalarToNextPow2(0)
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.clampScalar(0, S16, S32)
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.scalarize(0);
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}
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} else {
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getActionDefinitionsBuilder({G_SMIN, G_SMAX, G_UMIN, G_UMAX})
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.legalFor({S32})
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.clampScalar(0, S32, S32)
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.widenScalarToNextPow2(0)
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.scalarize(0);
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}
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auto smallerThan = [](unsigned TypeIdx0, unsigned TypeIdx1) {
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return [=](const LegalityQuery &Query) {
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return Query.Types[TypeIdx0].getSizeInBits() <
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Query.Types[TypeIdx1].getSizeInBits();
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};
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};
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auto greaterThan = [](unsigned TypeIdx0, unsigned TypeIdx1) {
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return [=](const LegalityQuery &Query) {
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return Query.Types[TypeIdx0].getSizeInBits() >
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Query.Types[TypeIdx1].getSizeInBits();
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};
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};
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getActionDefinitionsBuilder(G_INTTOPTR)
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// List the common cases
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.legalForCartesianProduct(AddrSpaces64, {S64})
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.legalForCartesianProduct(AddrSpaces32, {S32})
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.scalarize(0)
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// Accept any address space as long as the size matches
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.legalIf(sameSize(0, 1))
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.widenScalarIf(smallerThan(1, 0),
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[](const LegalityQuery &Query) {
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return std::make_pair(1, LLT::scalar(Query.Types[0].getSizeInBits()));
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})
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.narrowScalarIf(greaterThan(1, 0),
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[](const LegalityQuery &Query) {
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return std::make_pair(1, LLT::scalar(Query.Types[0].getSizeInBits()));
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});
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getActionDefinitionsBuilder(G_PTRTOINT)
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// List the common cases
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.legalForCartesianProduct(AddrSpaces64, {S64})
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.legalForCartesianProduct(AddrSpaces32, {S32})
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.scalarize(0)
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// Accept any address space as long as the size matches
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.legalIf(sameSize(0, 1))
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.widenScalarIf(smallerThan(0, 1),
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[](const LegalityQuery &Query) {
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return std::make_pair(0, LLT::scalar(Query.Types[1].getSizeInBits()));
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})
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.narrowScalarIf(
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greaterThan(0, 1),
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[](const LegalityQuery &Query) {
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return std::make_pair(0, LLT::scalar(Query.Types[1].getSizeInBits()));
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});
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if (ST.hasFlatAddressSpace()) {
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getActionDefinitionsBuilder(G_ADDRSPACE_CAST)
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.scalarize(0)
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.custom();
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}
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|
|
getActionDefinitionsBuilder({G_LOAD, G_STORE})
|
|
.narrowScalarIf([](const LegalityQuery &Query) {
|
|
unsigned Size = Query.Types[0].getSizeInBits();
|
|
unsigned MemSize = Query.MMODescrs[0].SizeInBits;
|
|
return (Size > 32 && MemSize < Size);
|
|
},
|
|
[](const LegalityQuery &Query) {
|
|
return std::make_pair(0, LLT::scalar(32));
|
|
})
|
|
.fewerElementsIf([=, &ST](const LegalityQuery &Query) {
|
|
unsigned MemSize = Query.MMODescrs[0].SizeInBits;
|
|
return (MemSize == 96) &&
|
|
Query.Types[0].isVector() &&
|
|
!ST.hasDwordx3LoadStores();
|
|
},
|
|
[=](const LegalityQuery &Query) {
|
|
return std::make_pair(0, V2S32);
|
|
})
|
|
.legalIf([=, &ST](const LegalityQuery &Query) {
|
|
const LLT &Ty0 = Query.Types[0];
|
|
|
|
unsigned Size = Ty0.getSizeInBits();
|
|
unsigned MemSize = Query.MMODescrs[0].SizeInBits;
|
|
if (Size < 32 || (Size > 32 && MemSize < Size))
|
|
return false;
|
|
|
|
if (Ty0.isVector() && Size != MemSize)
|
|
return false;
|
|
|
|
// TODO: Decompose private loads into 4-byte components.
|
|
// TODO: Illegal flat loads on SI
|
|
switch (MemSize) {
|
|
case 8:
|
|
case 16:
|
|
return Size == 32;
|
|
case 32:
|
|
case 64:
|
|
case 128:
|
|
return true;
|
|
|
|
case 96:
|
|
return ST.hasDwordx3LoadStores();
|
|
|
|
case 256:
|
|
case 512:
|
|
// TODO: constant loads
|
|
default:
|
|
return false;
|
|
}
|
|
})
|
|
.clampScalar(0, S32, S64);
|
|
|
|
|
|
// FIXME: Handle alignment requirements.
|
|
auto &ExtLoads = getActionDefinitionsBuilder({G_SEXTLOAD, G_ZEXTLOAD})
|
|
.legalForTypesWithMemDesc({
|
|
{S32, GlobalPtr, 8, 8},
|
|
{S32, GlobalPtr, 16, 8},
|
|
{S32, LocalPtr, 8, 8},
|
|
{S32, LocalPtr, 16, 8},
|
|
{S32, PrivatePtr, 8, 8},
|
|
{S32, PrivatePtr, 16, 8}});
|
|
if (ST.hasFlatAddressSpace()) {
|
|
ExtLoads.legalForTypesWithMemDesc({{S32, FlatPtr, 8, 8},
|
|
{S32, FlatPtr, 16, 8}});
|
|
}
|
|
|
|
ExtLoads.clampScalar(0, S32, S32)
|
|
.widenScalarToNextPow2(0)
|
|
.unsupportedIfMemSizeNotPow2()
|
|
.lower();
|
|
|
|
auto &Atomics = getActionDefinitionsBuilder(
|
|
{G_ATOMICRMW_XCHG, G_ATOMICRMW_ADD, G_ATOMICRMW_SUB,
|
|
G_ATOMICRMW_AND, G_ATOMICRMW_OR, G_ATOMICRMW_XOR,
|
|
G_ATOMICRMW_MAX, G_ATOMICRMW_MIN, G_ATOMICRMW_UMAX,
|
|
G_ATOMICRMW_UMIN, G_ATOMIC_CMPXCHG})
|
|
.legalFor({{S32, GlobalPtr}, {S32, LocalPtr},
|
|
{S64, GlobalPtr}, {S64, LocalPtr}});
|
|
if (ST.hasFlatAddressSpace()) {
|
|
Atomics.legalFor({{S32, FlatPtr}, {S64, FlatPtr}});
|
|
}
|
|
|
|
// TODO: Pointer types, any 32-bit or 64-bit vector
|
|
getActionDefinitionsBuilder(G_SELECT)
|
|
.legalForCartesianProduct({S32, S64, V2S32, V2S16, V4S16,
|
|
GlobalPtr, LocalPtr, FlatPtr, PrivatePtr,
|
|
LLT::vector(2, LocalPtr), LLT::vector(2, PrivatePtr)}, {S1})
|
|
.clampScalar(0, S32, S64)
|
|
.moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
|
|
.fewerElementsIf(numElementsNotEven(0), scalarize(0))
|
|
.scalarize(1)
|
|
.clampMaxNumElements(0, S32, 2)
|
|
.clampMaxNumElements(0, LocalPtr, 2)
|
|
.clampMaxNumElements(0, PrivatePtr, 2)
|
|
.scalarize(0)
|
|
.widenScalarToNextPow2(0)
|
|
.legalIf(all(isPointer(0), typeIs(1, S1)));
|
|
|
|
// TODO: Only the low 4/5/6 bits of the shift amount are observed, so we can
|
|
// be more flexible with the shift amount type.
|
|
auto &Shifts = getActionDefinitionsBuilder({G_SHL, G_LSHR, G_ASHR})
|
|
.legalFor({{S32, S32}, {S64, S32}});
|
|
if (ST.has16BitInsts()) {
|
|
if (ST.hasVOP3PInsts()) {
|
|
Shifts.legalFor({{S16, S32}, {S16, S16}, {V2S16, V2S16}})
|
|
.clampMaxNumElements(0, S16, 2);
|
|
} else
|
|
Shifts.legalFor({{S16, S32}, {S16, S16}});
|
|
|
|
Shifts.clampScalar(1, S16, S32);
|
|
Shifts.clampScalar(0, S16, S64);
|
|
Shifts.widenScalarToNextPow2(0, 16);
|
|
} else {
|
|
// Make sure we legalize the shift amount type first, as the general
|
|
// expansion for the shifted type will produce much worse code if it hasn't
|
|
// been truncated already.
|
|
Shifts.clampScalar(1, S32, S32);
|
|
Shifts.clampScalar(0, S32, S64);
|
|
Shifts.widenScalarToNextPow2(0, 32);
|
|
}
|
|
Shifts.scalarize(0);
|
|
|
|
for (unsigned Op : {G_EXTRACT_VECTOR_ELT, G_INSERT_VECTOR_ELT}) {
|
|
unsigned VecTypeIdx = Op == G_EXTRACT_VECTOR_ELT ? 1 : 0;
|
|
unsigned EltTypeIdx = Op == G_EXTRACT_VECTOR_ELT ? 0 : 1;
|
|
unsigned IdxTypeIdx = 2;
|
|
|
|
getActionDefinitionsBuilder(Op)
|
|
.legalIf([=](const LegalityQuery &Query) {
|
|
const LLT &VecTy = Query.Types[VecTypeIdx];
|
|
const LLT &IdxTy = Query.Types[IdxTypeIdx];
|
|
return VecTy.getSizeInBits() % 32 == 0 &&
|
|
VecTy.getSizeInBits() <= 512 &&
|
|
IdxTy.getSizeInBits() == 32;
|
|
})
|
|
.clampScalar(EltTypeIdx, S32, S64)
|
|
.clampScalar(VecTypeIdx, S32, S64)
|
|
.clampScalar(IdxTypeIdx, S32, S32);
|
|
}
|
|
|
|
getActionDefinitionsBuilder(G_EXTRACT_VECTOR_ELT)
|
|
.unsupportedIf([=](const LegalityQuery &Query) {
|
|
const LLT &EltTy = Query.Types[1].getElementType();
|
|
return Query.Types[0] != EltTy;
|
|
});
|
|
|
|
for (unsigned Op : {G_EXTRACT, G_INSERT}) {
|
|
unsigned BigTyIdx = Op == G_EXTRACT ? 1 : 0;
|
|
unsigned LitTyIdx = Op == G_EXTRACT ? 0 : 1;
|
|
|
|
// FIXME: Doesn't handle extract of illegal sizes.
|
|
getActionDefinitionsBuilder(Op)
|
|
.legalIf([=](const LegalityQuery &Query) {
|
|
const LLT BigTy = Query.Types[BigTyIdx];
|
|
const LLT LitTy = Query.Types[LitTyIdx];
|
|
return (BigTy.getSizeInBits() % 32 == 0) &&
|
|
(LitTy.getSizeInBits() % 16 == 0);
|
|
})
|
|
.widenScalarIf(
|
|
[=](const LegalityQuery &Query) {
|
|
const LLT BigTy = Query.Types[BigTyIdx];
|
|
return (BigTy.getScalarSizeInBits() < 16);
|
|
},
|
|
LegalizeMutations::widenScalarOrEltToNextPow2(BigTyIdx, 16))
|
|
.widenScalarIf(
|
|
[=](const LegalityQuery &Query) {
|
|
const LLT LitTy = Query.Types[LitTyIdx];
|
|
return (LitTy.getScalarSizeInBits() < 16);
|
|
},
|
|
LegalizeMutations::widenScalarOrEltToNextPow2(LitTyIdx, 16))
|
|
.moreElementsIf(isSmallOddVector(BigTyIdx), oneMoreElement(BigTyIdx))
|
|
.widenScalarToNextPow2(BigTyIdx, 32);
|
|
|
|
}
|
|
|
|
// TODO: vectors of pointers
|
|
getActionDefinitionsBuilder(G_BUILD_VECTOR)
|
|
.legalForCartesianProduct(AllS32Vectors, {S32})
|
|
.legalForCartesianProduct(AllS64Vectors, {S64})
|
|
.clampNumElements(0, V16S32, V16S32)
|
|
.clampNumElements(0, V2S64, V8S64)
|
|
.minScalarSameAs(1, 0)
|
|
// FIXME: Sort of a hack to make progress on other legalizations.
|
|
.legalIf([=](const LegalityQuery &Query) {
|
|
return Query.Types[0].getScalarSizeInBits() <= 32 ||
|
|
Query.Types[0].getScalarSizeInBits() == 64;
|
|
});
|
|
|
|
// TODO: Support any combination of v2s32
|
|
getActionDefinitionsBuilder(G_CONCAT_VECTORS)
|
|
.legalFor({{V4S32, V2S32},
|
|
{V8S32, V2S32},
|
|
{V8S32, V4S32},
|
|
{V4S64, V2S64},
|
|
{V4S16, V2S16},
|
|
{V8S16, V2S16},
|
|
{V8S16, V4S16},
|
|
{LLT::vector(4, LocalPtr), LLT::vector(2, LocalPtr)},
|
|
{LLT::vector(4, PrivatePtr), LLT::vector(2, PrivatePtr)}});
|
|
|
|
// Merge/Unmerge
|
|
for (unsigned Op : {G_MERGE_VALUES, G_UNMERGE_VALUES}) {
|
|
unsigned BigTyIdx = Op == G_MERGE_VALUES ? 0 : 1;
|
|
unsigned LitTyIdx = Op == G_MERGE_VALUES ? 1 : 0;
|
|
|
|
auto notValidElt = [=](const LegalityQuery &Query, unsigned TypeIdx) {
|
|
const LLT &Ty = Query.Types[TypeIdx];
|
|
if (Ty.isVector()) {
|
|
const LLT &EltTy = Ty.getElementType();
|
|
if (EltTy.getSizeInBits() < 8 || EltTy.getSizeInBits() > 64)
|
|
return true;
|
|
if (!isPowerOf2_32(EltTy.getSizeInBits()))
|
|
return true;
|
|
}
|
|
return false;
|
|
};
|
|
|
|
getActionDefinitionsBuilder(Op)
|
|
.widenScalarToNextPow2(LitTyIdx, /*Min*/ 16)
|
|
// Clamp the little scalar to s8-s256 and make it a power of 2. It's not
|
|
// worth considering the multiples of 64 since 2*192 and 2*384 are not
|
|
// valid.
|
|
.clampScalar(LitTyIdx, S16, S256)
|
|
.widenScalarToNextPow2(LitTyIdx, /*Min*/ 32)
|
|
|
|
// Break up vectors with weird elements into scalars
|
|
.fewerElementsIf(
|
|
[=](const LegalityQuery &Query) { return notValidElt(Query, 0); },
|
|
scalarize(0))
|
|
.fewerElementsIf(
|
|
[=](const LegalityQuery &Query) { return notValidElt(Query, 1); },
|
|
scalarize(1))
|
|
.clampScalar(BigTyIdx, S32, S512)
|
|
.widenScalarIf(
|
|
[=](const LegalityQuery &Query) {
|
|
const LLT &Ty = Query.Types[BigTyIdx];
|
|
return !isPowerOf2_32(Ty.getSizeInBits()) &&
|
|
Ty.getSizeInBits() % 16 != 0;
|
|
},
|
|
[=](const LegalityQuery &Query) {
|
|
// Pick the next power of 2, or a multiple of 64 over 128.
|
|
// Whichever is smaller.
|
|
const LLT &Ty = Query.Types[BigTyIdx];
|
|
unsigned NewSizeInBits = 1 << Log2_32_Ceil(Ty.getSizeInBits() + 1);
|
|
if (NewSizeInBits >= 256) {
|
|
unsigned RoundedTo = alignTo<64>(Ty.getSizeInBits() + 1);
|
|
if (RoundedTo < NewSizeInBits)
|
|
NewSizeInBits = RoundedTo;
|
|
}
|
|
return std::make_pair(BigTyIdx, LLT::scalar(NewSizeInBits));
|
|
})
|
|
.legalIf([=](const LegalityQuery &Query) {
|
|
const LLT &BigTy = Query.Types[BigTyIdx];
|
|
const LLT &LitTy = Query.Types[LitTyIdx];
|
|
|
|
if (BigTy.isVector() && BigTy.getSizeInBits() < 32)
|
|
return false;
|
|
if (LitTy.isVector() && LitTy.getSizeInBits() < 32)
|
|
return false;
|
|
|
|
return BigTy.getSizeInBits() % 16 == 0 &&
|
|
LitTy.getSizeInBits() % 16 == 0 &&
|
|
BigTy.getSizeInBits() <= 512;
|
|
})
|
|
// Any vectors left are the wrong size. Scalarize them.
|
|
.scalarize(0)
|
|
.scalarize(1);
|
|
}
|
|
|
|
computeTables();
|
|
verify(*ST.getInstrInfo());
|
|
}
|
|
|
|
bool AMDGPULegalizerInfo::legalizeCustom(MachineInstr &MI,
|
|
MachineRegisterInfo &MRI,
|
|
MachineIRBuilder &MIRBuilder,
|
|
GISelChangeObserver &Observer) const {
|
|
switch (MI.getOpcode()) {
|
|
case TargetOpcode::G_ADDRSPACE_CAST:
|
|
return legalizeAddrSpaceCast(MI, MRI, MIRBuilder);
|
|
case TargetOpcode::G_FRINT:
|
|
return legalizeFrint(MI, MRI, MIRBuilder);
|
|
case TargetOpcode::G_FCEIL:
|
|
return legalizeFceil(MI, MRI, MIRBuilder);
|
|
case TargetOpcode::G_INTRINSIC_TRUNC:
|
|
return legalizeIntrinsicTrunc(MI, MRI, MIRBuilder);
|
|
case TargetOpcode::G_SITOFP:
|
|
return legalizeITOFP(MI, MRI, MIRBuilder, true);
|
|
case TargetOpcode::G_UITOFP:
|
|
return legalizeITOFP(MI, MRI, MIRBuilder, false);
|
|
default:
|
|
return false;
|
|
}
|
|
|
|
llvm_unreachable("expected switch to return");
|
|
}
|
|
|
|
unsigned AMDGPULegalizerInfo::getSegmentAperture(
|
|
unsigned AS,
|
|
MachineRegisterInfo &MRI,
|
|
MachineIRBuilder &MIRBuilder) const {
|
|
MachineFunction &MF = MIRBuilder.getMF();
|
|
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
|
|
const LLT S32 = LLT::scalar(32);
|
|
|
|
if (ST.hasApertureRegs()) {
|
|
// FIXME: Use inline constants (src_{shared, private}_base) instead of
|
|
// getreg.
|
|
unsigned Offset = AS == AMDGPUAS::LOCAL_ADDRESS ?
|
|
AMDGPU::Hwreg::OFFSET_SRC_SHARED_BASE :
|
|
AMDGPU::Hwreg::OFFSET_SRC_PRIVATE_BASE;
|
|
unsigned WidthM1 = AS == AMDGPUAS::LOCAL_ADDRESS ?
|
|
AMDGPU::Hwreg::WIDTH_M1_SRC_SHARED_BASE :
|
|
AMDGPU::Hwreg::WIDTH_M1_SRC_PRIVATE_BASE;
|
|
unsigned Encoding =
|
|
AMDGPU::Hwreg::ID_MEM_BASES << AMDGPU::Hwreg::ID_SHIFT_ |
|
|
Offset << AMDGPU::Hwreg::OFFSET_SHIFT_ |
|
|
WidthM1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_;
|
|
|
|
unsigned ApertureReg = MRI.createGenericVirtualRegister(S32);
|
|
unsigned GetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
|
|
|
|
MIRBuilder.buildInstr(AMDGPU::S_GETREG_B32)
|
|
.addDef(GetReg)
|
|
.addImm(Encoding);
|
|
MRI.setType(GetReg, S32);
|
|
|
|
auto ShiftAmt = MIRBuilder.buildConstant(S32, WidthM1 + 1);
|
|
MIRBuilder.buildInstr(TargetOpcode::G_SHL)
|
|
.addDef(ApertureReg)
|
|
.addUse(GetReg)
|
|
.addUse(ShiftAmt.getReg(0));
|
|
|
|
return ApertureReg;
|
|
}
|
|
|
|
unsigned QueuePtr = MRI.createGenericVirtualRegister(
|
|
LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
|
|
|
|
// FIXME: Placeholder until we can track the input registers.
|
|
MIRBuilder.buildConstant(QueuePtr, 0xdeadbeef);
|
|
|
|
// Offset into amd_queue_t for group_segment_aperture_base_hi /
|
|
// private_segment_aperture_base_hi.
|
|
uint32_t StructOffset = (AS == AMDGPUAS::LOCAL_ADDRESS) ? 0x40 : 0x44;
|
|
|
|
// FIXME: Don't use undef
|
|
Value *V = UndefValue::get(PointerType::get(
|
|
Type::getInt8Ty(MF.getFunction().getContext()),
|
|
AMDGPUAS::CONSTANT_ADDRESS));
|
|
|
|
MachinePointerInfo PtrInfo(V, StructOffset);
|
|
MachineMemOperand *MMO = MF.getMachineMemOperand(
|
|
PtrInfo,
|
|
MachineMemOperand::MOLoad |
|
|
MachineMemOperand::MODereferenceable |
|
|
MachineMemOperand::MOInvariant,
|
|
4,
|
|
MinAlign(64, StructOffset));
|
|
|
|
unsigned LoadResult = MRI.createGenericVirtualRegister(S32);
|
|
unsigned LoadAddr = AMDGPU::NoRegister;
|
|
|
|
MIRBuilder.materializeGEP(LoadAddr, QueuePtr, LLT::scalar(64), StructOffset);
|
|
MIRBuilder.buildLoad(LoadResult, LoadAddr, *MMO);
|
|
return LoadResult;
|
|
}
|
|
|
|
bool AMDGPULegalizerInfo::legalizeAddrSpaceCast(
|
|
MachineInstr &MI, MachineRegisterInfo &MRI,
|
|
MachineIRBuilder &MIRBuilder) const {
|
|
MachineFunction &MF = MIRBuilder.getMF();
|
|
|
|
MIRBuilder.setInstr(MI);
|
|
|
|
unsigned Dst = MI.getOperand(0).getReg();
|
|
unsigned Src = MI.getOperand(1).getReg();
|
|
|
|
LLT DstTy = MRI.getType(Dst);
|
|
LLT SrcTy = MRI.getType(Src);
|
|
unsigned DestAS = DstTy.getAddressSpace();
|
|
unsigned SrcAS = SrcTy.getAddressSpace();
|
|
|
|
// TODO: Avoid reloading from the queue ptr for each cast, or at least each
|
|
// vector element.
|
|
assert(!DstTy.isVector());
|
|
|
|
const AMDGPUTargetMachine &TM
|
|
= static_cast<const AMDGPUTargetMachine &>(MF.getTarget());
|
|
|
|
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
|
|
if (ST.getTargetLowering()->isNoopAddrSpaceCast(SrcAS, DestAS)) {
|
|
MI.setDesc(MIRBuilder.getTII().get(TargetOpcode::G_BITCAST));
|
|
return true;
|
|
}
|
|
|
|
if (SrcAS == AMDGPUAS::FLAT_ADDRESS) {
|
|
assert(DestAS == AMDGPUAS::LOCAL_ADDRESS ||
|
|
DestAS == AMDGPUAS::PRIVATE_ADDRESS);
|
|
unsigned NullVal = TM.getNullPointerValue(DestAS);
|
|
|
|
auto SegmentNull = MIRBuilder.buildConstant(DstTy, NullVal);
|
|
auto FlatNull = MIRBuilder.buildConstant(SrcTy, 0);
|
|
|
|
unsigned PtrLo32 = MRI.createGenericVirtualRegister(DstTy);
|
|
|
|
// Extract low 32-bits of the pointer.
|
|
MIRBuilder.buildExtract(PtrLo32, Src, 0);
|
|
|
|
unsigned CmpRes = MRI.createGenericVirtualRegister(LLT::scalar(1));
|
|
MIRBuilder.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, FlatNull.getReg(0));
|
|
MIRBuilder.buildSelect(Dst, CmpRes, PtrLo32, SegmentNull.getReg(0));
|
|
|
|
MI.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
assert(SrcAS == AMDGPUAS::LOCAL_ADDRESS ||
|
|
SrcAS == AMDGPUAS::PRIVATE_ADDRESS);
|
|
|
|
auto SegmentNull =
|
|
MIRBuilder.buildConstant(SrcTy, TM.getNullPointerValue(SrcAS));
|
|
auto FlatNull =
|
|
MIRBuilder.buildConstant(DstTy, TM.getNullPointerValue(DestAS));
|
|
|
|
unsigned ApertureReg = getSegmentAperture(DestAS, MRI, MIRBuilder);
|
|
|
|
unsigned CmpRes = MRI.createGenericVirtualRegister(LLT::scalar(1));
|
|
MIRBuilder.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, SegmentNull.getReg(0));
|
|
|
|
unsigned BuildPtr = MRI.createGenericVirtualRegister(DstTy);
|
|
|
|
// Coerce the type of the low half of the result so we can use merge_values.
|
|
unsigned SrcAsInt = MRI.createGenericVirtualRegister(LLT::scalar(32));
|
|
MIRBuilder.buildInstr(TargetOpcode::G_PTRTOINT)
|
|
.addDef(SrcAsInt)
|
|
.addUse(Src);
|
|
|
|
// TODO: Should we allow mismatched types but matching sizes in merges to
|
|
// avoid the ptrtoint?
|
|
MIRBuilder.buildMerge(BuildPtr, {SrcAsInt, ApertureReg});
|
|
MIRBuilder.buildSelect(Dst, CmpRes, BuildPtr, FlatNull.getReg(0));
|
|
|
|
MI.eraseFromParent();
|
|
return true;
|
|
}
|
|
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bool AMDGPULegalizerInfo::legalizeFrint(
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MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const {
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MIRBuilder.setInstr(MI);
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unsigned Src = MI.getOperand(1).getReg();
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LLT Ty = MRI.getType(Src);
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assert(Ty.isScalar() && Ty.getSizeInBits() == 64);
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APFloat C1Val(APFloat::IEEEdouble(), "0x1.0p+52");
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APFloat C2Val(APFloat::IEEEdouble(), "0x1.fffffffffffffp+51");
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auto C1 = MIRBuilder.buildFConstant(Ty, C1Val);
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auto CopySign = MIRBuilder.buildFCopysign(Ty, C1, Src);
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// TODO: Should this propagate fast-math-flags?
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auto Tmp1 = MIRBuilder.buildFAdd(Ty, Src, CopySign);
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auto Tmp2 = MIRBuilder.buildFSub(Ty, Tmp1, CopySign);
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auto C2 = MIRBuilder.buildFConstant(Ty, C2Val);
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auto Fabs = MIRBuilder.buildFAbs(Ty, Src);
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auto Cond = MIRBuilder.buildFCmp(CmpInst::FCMP_OGT, LLT::scalar(1), Fabs, C2);
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MIRBuilder.buildSelect(MI.getOperand(0).getReg(), Cond, Src, Tmp2);
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return true;
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}
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bool AMDGPULegalizerInfo::legalizeFceil(
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MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const {
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B.setInstr(MI);
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const LLT S1 = LLT::scalar(1);
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const LLT S64 = LLT::scalar(64);
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unsigned Src = MI.getOperand(1).getReg();
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assert(MRI.getType(Src) == S64);
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// result = trunc(src)
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// if (src > 0.0 && src != result)
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// result += 1.0
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auto Trunc = B.buildInstr(TargetOpcode::G_INTRINSIC_TRUNC, {S64}, {Src});
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const auto Zero = B.buildFConstant(S64, 0.0);
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const auto One = B.buildFConstant(S64, 1.0);
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auto Lt0 = B.buildFCmp(CmpInst::FCMP_OGT, S1, Src, Zero);
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auto NeTrunc = B.buildFCmp(CmpInst::FCMP_ONE, S1, Src, Trunc);
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auto And = B.buildAnd(S1, Lt0, NeTrunc);
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auto Add = B.buildSelect(S64, And, One, Zero);
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// TODO: Should this propagate fast-math-flags?
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B.buildFAdd(MI.getOperand(0).getReg(), Trunc, Add);
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return true;
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}
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static MachineInstrBuilder extractF64Exponent(unsigned Hi,
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MachineIRBuilder &B) {
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const unsigned FractBits = 52;
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const unsigned ExpBits = 11;
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LLT S32 = LLT::scalar(32);
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auto Const0 = B.buildConstant(S32, FractBits - 32);
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auto Const1 = B.buildConstant(S32, ExpBits);
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auto ExpPart = B.buildIntrinsic(Intrinsic::amdgcn_ubfe, {S32}, false)
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.addUse(Const0.getReg(0))
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.addUse(Const1.getReg(0));
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return B.buildSub(S32, ExpPart, B.buildConstant(S32, 1023));
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}
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bool AMDGPULegalizerInfo::legalizeIntrinsicTrunc(
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MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const {
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B.setInstr(MI);
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const LLT S1 = LLT::scalar(1);
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const LLT S32 = LLT::scalar(32);
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const LLT S64 = LLT::scalar(64);
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unsigned Src = MI.getOperand(1).getReg();
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assert(MRI.getType(Src) == S64);
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// TODO: Should this use extract since the low half is unused?
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auto Unmerge = B.buildUnmerge({S32, S32}, Src);
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unsigned Hi = Unmerge.getReg(1);
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// Extract the upper half, since this is where we will find the sign and
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// exponent.
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auto Exp = extractF64Exponent(Hi, B);
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const unsigned FractBits = 52;
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// Extract the sign bit.
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const auto SignBitMask = B.buildConstant(S32, UINT32_C(1) << 31);
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auto SignBit = B.buildAnd(S32, Hi, SignBitMask);
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const auto FractMask = B.buildConstant(S64, (UINT64_C(1) << FractBits) - 1);
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const auto Zero32 = B.buildConstant(S32, 0);
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// Extend back to 64-bits.
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auto SignBit64 = B.buildMerge(S64, {Zero32.getReg(0), SignBit.getReg(0)});
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auto Shr = B.buildAShr(S64, FractMask, Exp);
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auto Not = B.buildNot(S64, Shr);
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auto Tmp0 = B.buildAnd(S64, Src, Not);
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auto FiftyOne = B.buildConstant(S32, FractBits - 1);
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auto ExpLt0 = B.buildICmp(CmpInst::ICMP_SLT, S1, Exp, Zero32);
|
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auto ExpGt51 = B.buildICmp(CmpInst::ICMP_SGT, S1, Exp, FiftyOne);
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auto Tmp1 = B.buildSelect(S64, ExpLt0, SignBit64, Tmp0);
|
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B.buildSelect(MI.getOperand(0).getReg(), ExpGt51, Src, Tmp1);
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return true;
|
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}
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bool AMDGPULegalizerInfo::legalizeITOFP(
|
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MachineInstr &MI, MachineRegisterInfo &MRI,
|
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MachineIRBuilder &B, bool Signed) const {
|
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B.setInstr(MI);
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|
|
unsigned Dst = MI.getOperand(0).getReg();
|
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unsigned Src = MI.getOperand(1).getReg();
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|
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const LLT S64 = LLT::scalar(64);
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|
const LLT S32 = LLT::scalar(32);
|
|
|
|
assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S64);
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auto Unmerge = B.buildUnmerge({S32, S32}, Src);
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|
|
|
auto CvtHi = Signed ?
|
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B.buildSITOFP(S64, Unmerge.getReg(1)) :
|
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B.buildUITOFP(S64, Unmerge.getReg(1));
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|
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auto CvtLo = B.buildUITOFP(S64, Unmerge.getReg(0));
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|
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auto ThirtyTwo = B.buildConstant(S32, 32);
|
|
auto LdExp = B.buildIntrinsic(Intrinsic::amdgcn_ldexp, {S64}, false)
|
|
.addUse(CvtHi.getReg(0))
|
|
.addUse(ThirtyTwo.getReg(0));
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|
|
|
// TODO: Should this propagate fast-math-flags?
|
|
B.buildFAdd(Dst, LdExp, CvtLo);
|
|
MI.eraseFromParent();
|
|
return true;
|
|
}
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