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974a445bd9
subsequent changes are easier to review. About to fix some layering issues, and wanted to separate out the necessary churn. Also comment and sink the include of "Windows.h" in three .inc files to match the usage in Memory.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198685 91177308-0d34-0410-b5e6-96231b3b80d8
224 lines
10 KiB
C++
224 lines
10 KiB
C++
//===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Hexagon implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef HexagonINSTRUCTIONINFO_H
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#define HexagonINSTRUCTIONINFO_H
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#include "HexagonRegisterInfo.h"
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#include "MCTargetDesc/HexagonBaseInfo.h"
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#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "HexagonGenInstrInfo.inc"
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namespace llvm {
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class HexagonInstrInfo : public HexagonGenInstrInfo {
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virtual void anchor();
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const HexagonRegisterInfo RI;
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const HexagonSubtarget &Subtarget;
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typedef unsigned Opcode_t;
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public:
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explicit HexagonInstrInfo(HexagonSubtarget &ST);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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virtual const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const;
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const;
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virtual bool analyzeCompare(const MachineInstr *MI,
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unsigned &SrcReg, unsigned &SrcReg2,
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int &Mask, int &Value) const;
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const;
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr* MI,
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const SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const;
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virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr* MI,
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const SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const {
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return 0;
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}
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unsigned createVR(MachineFunction* MF, MVT VT) const;
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virtual bool isBranch(const MachineInstr *MI) const;
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virtual bool isPredicable(MachineInstr *MI) const;
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virtual bool
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PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Cond) const;
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virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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unsigned ExtraPredCycles,
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const BranchProbability &Probability) const;
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virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
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unsigned NumTCycles, unsigned ExtraTCycles,
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MachineBasicBlock &FMBB,
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unsigned NumFCycles, unsigned ExtraFCycles,
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const BranchProbability &Probability) const;
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virtual bool isPredicated(const MachineInstr *MI) const;
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virtual bool isPredicated(unsigned Opcode) const;
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virtual bool isPredicatedTrue(const MachineInstr *MI) const;
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virtual bool isPredicatedTrue(unsigned Opcode) const;
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virtual bool isPredicatedNew(const MachineInstr *MI) const;
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virtual bool isPredicatedNew(unsigned Opcode) const;
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virtual bool DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const;
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virtual bool
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SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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const SmallVectorImpl<MachineOperand> &Pred2) const;
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virtual bool
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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virtual bool
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isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumCycles,
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const BranchProbability &Probability) const;
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virtual DFAPacketizer*
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CreateTargetScheduleState(const TargetMachine *TM,
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const ScheduleDAG *DAG) const;
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virtual bool isSchedulingBoundary(const MachineInstr *MI,
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const MachineBasicBlock *MBB,
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const MachineFunction &MF) const;
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bool isValidOffset(const int Opcode, const int Offset) const;
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bool isValidAutoIncImm(const EVT VT, const int Offset) const;
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bool isMemOp(const MachineInstr *MI) const;
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bool isSpillPredRegOp(const MachineInstr *MI) const;
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bool isU6_3Immediate(const int value) const;
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bool isU6_2Immediate(const int value) const;
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bool isU6_1Immediate(const int value) const;
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bool isU6_0Immediate(const int value) const;
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bool isS4_3Immediate(const int value) const;
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bool isS4_2Immediate(const int value) const;
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bool isS4_1Immediate(const int value) const;
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bool isS4_0Immediate(const int value) const;
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bool isS12_Immediate(const int value) const;
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bool isU6_Immediate(const int value) const;
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bool isS8_Immediate(const int value) const;
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bool isS6_Immediate(const int value) const;
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bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const;
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bool isConditionalTransfer(const MachineInstr* MI) const;
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bool isConditionalALU32 (const MachineInstr* MI) const;
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bool isConditionalLoad (const MachineInstr* MI) const;
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bool isConditionalStore(const MachineInstr* MI) const;
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bool isNewValueInst(const MachineInstr* MI) const;
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bool isNewValue(const MachineInstr* MI) const;
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bool isDotNewInst(const MachineInstr* MI) const;
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int GetDotOldOp(const int opc) const;
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int GetDotNewOp(const MachineInstr* MI) const;
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int GetDotNewPredOp(MachineInstr *MI,
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const MachineBranchProbabilityInfo
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*MBPI) const;
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bool mayBeNewStore(const MachineInstr* MI) const;
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bool isDeallocRet(const MachineInstr *MI) const;
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unsigned getInvertedPredicatedOpcode(const int Opc) const;
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bool isExtendable(const MachineInstr* MI) const;
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bool isExtended(const MachineInstr* MI) const;
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bool isPostIncrement(const MachineInstr* MI) const;
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bool isNewValueStore(const MachineInstr* MI) const;
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bool isNewValueStore(unsigned Opcode) const;
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bool isNewValueJump(const MachineInstr* MI) const;
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bool isNewValueJumpCandidate(const MachineInstr *MI) const;
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void immediateExtend(MachineInstr *MI) const;
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bool isConstExtended(MachineInstr *MI) const;
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int getDotNewPredJumpOp(MachineInstr *MI,
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const MachineBranchProbabilityInfo *MBPI) const;
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unsigned getAddrMode(const MachineInstr* MI) const;
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bool isOperandExtended(const MachineInstr *MI,
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unsigned short OperandNum) const;
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unsigned short getCExtOpNum(const MachineInstr *MI) const;
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int getMinValue(const MachineInstr *MI) const;
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int getMaxValue(const MachineInstr *MI) const;
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bool NonExtEquivalentExists (const MachineInstr *MI) const;
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short getNonExtOpcode(const MachineInstr *MI) const;
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bool PredOpcodeHasJMP_c(Opcode_t Opcode) const;
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bool PredOpcodeHasNot(Opcode_t Opcode) const;
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private:
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int getMatchingCondBranchOpcode(int Opc, bool sense) const;
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};
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}
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#endif
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