mirror of
https://github.com/RPCS3/llvm.git
synced 2024-12-29 16:04:33 +00:00
4a51708448
Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well. Also fix isel hook to correctly set the optional operand. rdar://10073745 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139157 91177308-0d34-0410-b5e6-96231b3b80d8
48 lines
825 B
LLVM
48 lines
825 B
LLVM
; RUN: llc < %s -march=arm | FileCheck %s
|
|
|
|
define i64 @f1(i64 %a, i64 %b) {
|
|
; CHECK: f1:
|
|
; CHECK: subs r
|
|
; CHECK: sbc r
|
|
entry:
|
|
%tmp = sub i64 %a, %b
|
|
ret i64 %tmp
|
|
}
|
|
|
|
define i64 @f2(i64 %a, i64 %b) {
|
|
; CHECK: f2:
|
|
; CHECK: adc r
|
|
; CHECK: subs r
|
|
; CHECK: sbc r
|
|
entry:
|
|
%tmp1 = shl i64 %a, 1
|
|
%tmp2 = sub i64 %tmp1, %b
|
|
ret i64 %tmp2
|
|
}
|
|
|
|
; add with live carry
|
|
define i64 @f3(i32 %al, i32 %bl) {
|
|
; CHECK: f3:
|
|
; CHECK: adds r
|
|
; CHECK: adc r
|
|
entry:
|
|
; unsigned wide add
|
|
%aw = zext i32 %al to i64
|
|
%bw = zext i32 %bl to i64
|
|
%cw = add i64 %aw, %bw
|
|
; ch == carry bit
|
|
%ch = lshr i64 %cw, 32
|
|
%dw = add i64 %ch, %bw
|
|
ret i64 %dw
|
|
}
|
|
|
|
; rdar://10073745
|
|
define i64 @f4(i64 %x) nounwind readnone {
|
|
entry:
|
|
; CHECK: f4:
|
|
; CHECK: rsbs r
|
|
; CHECK: rsc r
|
|
%0 = sub nsw i64 0, %x
|
|
ret i64 %0
|
|
}
|