Matt Arsenault d82cfba790 AMDGPU: Fold fneg into fmed3 ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@339821 91177308-0d34-0410-b5e6-96231b3b80d8

2018-08-15 21:46:27 +00:00

..

AArch64

[AArch64] add tests for poor vector intrinsic lowering via legalization (PR38527); NFC

2018-08-15 17:06:21 +00:00

AMDGPU

AMDGPU: Fold fneg into fmed3

2018-08-15 21:46:27 +00:00

ARC

[ARC] Add ARC backend.

2017-08-24 15:40:33 +00:00

ARM

Revert "[ARM] Allow signed icmps in ARMCodeGenPrepare"

2018-08-15 20:09:35 +00:00

AVR

[AVR] Set trackLivenessAfterRegAlloc

2018-06-11 14:46:48 +00:00

BPF

bpf: add missing RegState to notify MachineInstr verifier necessary register usage

2018-07-27 16:58:52 +00:00

Generic

[DWARF] Unclamp line table version on Darwin for v5 and later.

2018-08-08 21:16:50 +00:00

Hexagon

[Hexagon] Map ISD::TRAP to J2_trap0(#0)

2018-08-09 18:03:45 +00:00

Inputs

…

Lanai

Remove SETCCE use from Lanai's backend

2018-06-03 12:56:24 +00:00

Mips

[mips] Handle branch expansion corner cases

2018-08-07 10:45:45 +00:00

MIR

[DebugInfo][X86] Add start-after flags to MIR tests

2018-07-12 14:36:48 +00:00

MSP430

Emit a left-shift instead of a power-of-two multiply for jump-tables

2018-05-16 08:58:26 +00:00

Nios2

[Nios2] Arithmetic instructions for R1 and R2 ISA.

2018-01-09 11:15:08 +00:00

NVPTX

DAG: Check no-signed-zeros instead of unsafe-fp-math

2018-08-12 19:09:12 +00:00

PowerPC

[PowerPC] Enhance the selection(ISD::VSELECT) of vector type

2018-08-15 15:30:36 +00:00

RISCV

[RISCV] Fixed test case failure due to r338047

2018-07-31 00:36:28 +00:00

SPARC

Revert "[Sparc] Add support for the cycle counter available in GR740"

2018-08-13 14:18:09 +00:00

SystemZ

[RegisterCoalescer] Ensure that both registers have subranges if one does

2018-08-15 17:04:58 +00:00

Thumb

[ARM] Adjust AND immediates to make them cheaper to select.

2018-08-10 21:21:53 +00:00

Thumb2

[ARM] Treat cmn immediates as legal in isLegalICmpImmediate.

2018-07-10 23:44:37 +00:00

WebAssembly

[WebAssembly] SIMD replace_lane

2018-08-15 16:18:51 +00:00

WinCFGuard

Rename the cfguard module flag to cfguardtable

2018-08-10 09:48:53 +00:00

WinEH

[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.

2018-05-09 02:40:45 +00:00

X86

[X86] Improve AVX1 shuffle lowering for v8f32 shuffles where the low half comes from V1 and the high half comes from V2 and the halves do the same operation

2018-08-15 21:21:52 +00:00

XCore

[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)

2018-07-15 16:27:07 +00:00