Anna Thomas d89a69b5fd Revert "Invariant start/end intrinsics overloaded for address space" ...

This reverts commit r276316.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276320 91177308-0d34-0410-b5e6-96231b3b80d8

2016-07-21 19:06:28 +00:00

..

AArch64

[IRTranslator] Add G_SUB opcode.

2016-07-21 17:26:50 +00:00

AMDGPU

Revert "Invariant start/end intrinsics overloaded for address space"

2016-07-21 19:06:28 +00:00

ARM

[ARM] Skip inline asm memory operands in DAGToDAGISel

2016-07-20 09:48:24 +00:00

BPF

[BPF] Remove exit-on-error from tests (PR27768, PR27769)

2016-05-30 08:28:34 +00:00

Generic

Move mempcpy_call.ll to X86 subdirectory

2016-07-13 18:28:45 +00:00

Hexagon

[Hexagon] Handle returning small structures by value

2016-07-18 17:30:41 +00:00

Inputs

[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.

2016-04-15 15:57:41 +00:00

Lanai

[lanai] Use peephole optimizer to generate more conditional ALU operations.

2016-07-07 23:36:04 +00:00

Mips

Revert "RegScavenging: Add scavengeRegisterBackwards()"

2016-07-20 00:21:32 +00:00

MIR

GlobalISel: implement low-level type with just size & vector lanes.

2016-07-20 19:09:30 +00:00

MSP430

MSP430InstrInfo::loadRegFromStackSlot forgets to set register def.

2016-02-24 15:15:02 +00:00

NVPTX

[NVPTX] Enable the load-store vectorizer on nvptx.

2016-07-20 22:11:36 +00:00

PowerPC

Revert "RegScavenging: Add scavengeRegisterBackwards()"

2016-07-20 00:21:32 +00:00

SPARC

VirtRegMap: Replace some identity copies with KILL instructions.

2016-07-09 00:19:07 +00:00

SystemZ

Revert "RegScavenging: Add scavengeRegisterBackwards()"

2016-07-20 00:21:32 +00:00

Thumb

Revert "RegScavenging: Add scavengeRegisterBackwards()"

2016-07-20 00:21:32 +00:00

Thumb2

[Thumb] Reapply r272251 with a fix for PR28348 (mk 2)

2016-07-05 12:37:13 +00:00

WebAssembly

[WebAssembly] Emit type signatures for declared functions

2016-06-03 18:34:36 +00:00

WinEH

revert http://reviews.llvm.org/D21101

2016-06-30 17:52:24 +00:00

X86

[X86][SSE] Allow folding of store/zext with PEXTRW of 0'th element

2016-07-21 14:54:17 +00:00

XCore

IR: Introduce Module::global_objects().

2016-06-22 20:29:42 +00:00