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4c925c60eb
...namely LOAD AND ADD, LOAD AND AND, LOAD AND OR and LOAD AND EXCLUSIVE OR. LOAD AND ADD LOGICAL isn't really separately useful for LLVM. I'll look at adding reusing the CC results in new year. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197985 91177308-0d34-0410-b5e6-96231b3b80d8
65 lines
1.7 KiB
LLVM
65 lines
1.7 KiB
LLVM
; Test 32-bit atomic ORs, z196 version.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
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; Check OR of a variable.
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define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK-LABEL: f1:
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; CHECK: lao %r2, %r4, 0(%r3)
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; CHECK: br %r14
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%res = atomicrmw or i32 *%src, i32 %b seq_cst
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ret i32 %res
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}
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; Check OR of 1, which needs a temporary.
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define i32 @f2(i32 %dummy, i32 *%src) {
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; CHECK-LABEL: f2:
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; CHECK: lhi [[TMP:%r[0-5]]], 1
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; CHECK: lao %r2, [[TMP]], 0(%r3)
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; CHECK: br %r14
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%res = atomicrmw or i32 *%src, i32 1 seq_cst
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ret i32 %res
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}
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; Check the high end of the LAO range.
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define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK-LABEL: f3:
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; CHECK: lao %r2, %r4, 524284(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i32 131071
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%res = atomicrmw or i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check the next word up, which needs separate address logic.
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define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK-LABEL: f4:
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; CHECK: agfi %r3, 524288
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; CHECK: lao %r2, %r4, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i32 131072
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%res = atomicrmw or i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check the low end of the LAO range.
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define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK-LABEL: f5:
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; CHECK: lao %r2, %r4, -524288(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i32 -131072
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%res = atomicrmw or i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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; Check the next word down, which needs separate address logic.
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define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
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; CHECK-LABEL: f6:
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; CHECK: agfi %r3, -524292
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; CHECK: lao %r2, %r4, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i32 -131073
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%res = atomicrmw or i32 *%ptr, i32 %b seq_cst
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ret i32 %res
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}
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