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aa5b9c0f6f
be deleted. This will be reapplied as soon as possible and before the 3.6 branch date at any rate. Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reverts commits r215111, 215115, 215116, 215117, 215136. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215154 91177308-0d34-0410-b5e6-96231b3b80d8
102 lines
3.7 KiB
C++
102 lines
3.7 KiB
C++
//===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "SparcTargetMachine.h"
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#include "Sparc.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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extern "C" void LLVMInitializeSparcTarget() {
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// Register the target.
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RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget);
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RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target);
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}
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/// SparcTargetMachine ctor - Create an ILP32 architecture model
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///
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SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL,
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bool is64bit)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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Subtarget(TT, CPU, FS, *this, is64bit) {
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initAsmInfo();
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}
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namespace {
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/// Sparc Code Generator Pass Configuration Options.
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class SparcPassConfig : public TargetPassConfig {
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public:
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SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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SparcTargetMachine &getSparcTargetMachine() const {
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return getTM<SparcTargetMachine>();
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}
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bool addInstSelector() override;
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bool addPreEmitPass() override;
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};
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} // namespace
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TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new SparcPassConfig(this, PM);
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}
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bool SparcPassConfig::addInstSelector() {
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addPass(createSparcISelDag(getSparcTargetMachine()));
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return false;
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}
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bool SparcTargetMachine::addCodeEmitter(PassManagerBase &PM,
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JITCodeEmitter &JCE) {
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// Machine code emitter pass for Sparc.
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PM.add(createSparcJITCodeEmitterPass(*this, JCE));
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return false;
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}
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/// addPreEmitPass - This pass may be implemented by targets that want to run
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/// passes immediately before machine code is emitted. This should return
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/// true if -print-machineinstrs should print out the code after the passes.
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bool SparcPassConfig::addPreEmitPass(){
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addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
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return true;
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}
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void SparcV8TargetMachine::anchor() { }
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SparcV8TargetMachine::SparcV8TargetMachine(const Target &T,
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StringRef TT, StringRef CPU,
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StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
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}
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void SparcV9TargetMachine::anchor() { }
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SparcV9TargetMachine::SparcV9TargetMachine(const Target &T,
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StringRef TT, StringRef CPU,
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StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
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}
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