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5e487f8dc7
This teaches the AArch64 backend to deal with the operations required to deal with the operations on v4f16 and v8f16 which are exposed by NEON intrinsics, plus the add, sub, mul and div operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216555 91177308-0d34-0410-b5e6-96231b3b80d8
246 lines
12 KiB
TableGen
246 lines
12 KiB
TableGen
//=- AArch64CallingConv.td - Calling Conventions for AArch64 -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This describes the calling conventions for AArch64 architecture.
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//
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//===----------------------------------------------------------------------===//
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/// CCIfAlign - Match of the original alignment of the arg
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class CCIfAlign<string Align, CCAction A> :
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CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>;
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/// CCIfBigEndian - Match only if we're in big endian mode.
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class CCIfBigEndian<CCAction A> :
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CCIf<"State.getMachineFunction().getSubtarget().getDataLayout()->isBigEndian()", A>;
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//===----------------------------------------------------------------------===//
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// ARM AAPCS64 Calling Convention
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//===----------------------------------------------------------------------===//
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def CC_AArch64_AAPCS : CallingConv<[
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CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
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CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>,
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// Big endian vectors must be passed as if they were 1-element vectors so that
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// their lanes are in a consistent order.
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CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v8i8],
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CCBitConvertToType<f64>>>,
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CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
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CCBitConvertToType<f128>>>,
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// An SRet is passed in X8, not X0 like a normal pointer parameter.
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CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[X8], [W8]>>>,
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// Put ByVal arguments directly on the stack. Minimum size and alignment of a
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// slot is 64-bit.
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CCIfByVal<CCPassByVal<8, 8>>,
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// Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers,
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// up to eight each of GPR and FPR.
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CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
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CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
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[X0, X1, X2, X3, X4, X5, X6, X7]>>,
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// i128 is split to two i64s, we can't fit half to register X7.
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CCIfType<[i64], CCIfSplit<CCAssignToRegWithShadow<[X0, X2, X4, X6],
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[X0, X1, X3, X5]>>>,
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// i128 is split to two i64s, and its stack alignment is 16 bytes.
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CCIfType<[i64], CCIfSplit<CCAssignToStackWithShadow<8, 16, [X7]>>>,
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CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
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[W0, W1, W2, W3, W4, W5, W6, W7]>>,
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CCIfType<[f16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
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CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
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CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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// If more than will fit in registers, pass them on the stack instead.
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CCIfType<[i1, i8, i16, f16], CCAssignToStack<8, 8>>,
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CCIfType<[i32, f32], CCAssignToStack<8, 8>>,
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CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16],
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CCAssignToStack<8, 8>>,
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CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
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CCAssignToStack<16, 16>>
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]>;
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def RetCC_AArch64_AAPCS : CallingConv<[
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CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
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CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>,
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// Big endian vectors must be passed as if they were 1-element vectors so that
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// their lanes are in a consistent order.
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CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v8i8],
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CCBitConvertToType<f64>>>,
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CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
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CCBitConvertToType<f128>>>,
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CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
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[X0, X1, X2, X3, X4, X5, X6, X7]>>,
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CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
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[W0, W1, W2, W3, W4, W5, W6, W7]>>,
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CCIfType<[f16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
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CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
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CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>
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]>;
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// Darwin uses a calling convention which differs in only two ways
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// from the standard one at this level:
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// + i128s (i.e. split i64s) don't need even registers.
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// + Stack slots are sized as needed rather than being at least 64-bit.
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def CC_AArch64_DarwinPCS : CallingConv<[
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CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
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CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>,
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// An SRet is passed in X8, not X0 like a normal pointer parameter.
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CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[X8], [W8]>>>,
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// Put ByVal arguments directly on the stack. Minimum size and alignment of a
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// slot is 64-bit.
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CCIfByVal<CCPassByVal<8, 8>>,
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// Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers,
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// up to eight each of GPR and FPR.
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CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
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CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
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[X0, X1, X2, X3, X4, X5, X6, X7]>>,
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// i128 is split to two i64s, we can't fit half to register X7.
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CCIfType<[i64],
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CCIfSplit<CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6],
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[W0, W1, W2, W3, W4, W5, W6]>>>,
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// i128 is split to two i64s, and its stack alignment is 16 bytes.
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CCIfType<[i64], CCIfSplit<CCAssignToStackWithShadow<8, 16, [X7]>>>,
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CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
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[W0, W1, W2, W3, W4, W5, W6, W7]>>,
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CCIfType<[f16], CCAssignToRegWithShadow<[H0, H1, H2, H3, H4, H5, H6, H7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
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CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
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CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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// If more than will fit in registers, pass them on the stack instead.
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CCIf<"ValVT == MVT::i1 || ValVT == MVT::i8", CCAssignToStack<1, 1>>,
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CCIf<"ValVT == MVT::i16 || ValVT == MVT::f16", CCAssignToStack<2, 2>>,
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CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
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CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16],
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CCAssignToStack<8, 8>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
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CCAssignToStack<16, 16>>
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]>;
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def CC_AArch64_DarwinPCS_VarArg : CallingConv<[
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CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
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CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>,
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// Handle all scalar types as either i64 or f64.
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CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
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CCIfType<[f16, f32], CCPromoteToType<f64>>,
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// Everything is on the stack.
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// i128 is split to two i64s, and its stack alignment is 16 bytes.
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CCIfType<[i64], CCIfSplit<CCAssignToStack<8, 16>>>,
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CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
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CCAssignToStack<8, 8>>,
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CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
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CCAssignToStack<16, 16>>
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]>;
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// The WebKit_JS calling convention only passes the first argument (the callee)
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// in register and the remaining arguments on stack. We allow 32bit stack slots,
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// so that WebKit can write partial values in the stack and define the other
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// 32bit quantity as undef.
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def CC_AArch64_WebKit_JS : CallingConv<[
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// Handle i1, i8, i16, i32, and i64 passing in register X0 (W0).
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CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
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CCIfType<[i32], CCAssignToRegWithShadow<[W0], [X0]>>,
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CCIfType<[i64], CCAssignToRegWithShadow<[X0], [W0]>>,
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// Pass the remaining arguments on the stack instead.
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CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
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CCIfType<[i64, f64], CCAssignToStack<8, 8>>
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]>;
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def RetCC_AArch64_WebKit_JS : CallingConv<[
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CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
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[X0, X1, X2, X3, X4, X5, X6, X7]>>,
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CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
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[W0, W1, W2, W3, W4, W5, W6, W7]>>,
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CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
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[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>
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]>;
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// FIXME: LR is only callee-saved in the sense that *we* preserve it and are
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// presumably a callee to someone. External functions may not do so, but this
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// is currently safe since BL has LR as an implicit-def and what happens after a
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// tail call doesn't matter.
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//
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// It would be better to model its preservation semantics properly (create a
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// vreg on entry, use it in RET & tail call generation; make that vreg def if we
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// end up saving LR as part of a call frame). Watch this space...
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def CSR_AArch64_AAPCS : CalleeSavedRegs<(add LR, FP, X19, X20, X21, X22,
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X23, X24, X25, X26, X27, X28,
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D8, D9, D10, D11,
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D12, D13, D14, D15)>;
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// Constructors and destructors return 'this' in the iOS 64-bit C++ ABI; since
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// 'this' and the pointer return value are both passed in X0 in these cases,
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// this can be partially modelled by treating X0 as a callee-saved register;
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// only the resulting RegMask is used; the SaveList is ignored
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//
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// (For generic ARM 64-bit ABI code, clang will not generate constructors or
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// destructors with 'this' returns, so this RegMask will not be used in that
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// case)
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def CSR_AArch64_AAPCS_ThisReturn : CalleeSavedRegs<(add CSR_AArch64_AAPCS, X0)>;
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// The function used by Darwin to obtain the address of a thread-local variable
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// guarantees more than a normal AAPCS function. x16 and x17 are used on the
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// fast path for calculation, but other registers except X0 (argument/return)
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// and LR (it is a call, after all) are preserved.
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def CSR_AArch64_TLS_Darwin
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: CalleeSavedRegs<(add (sub (sequence "X%u", 1, 28), X16, X17),
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FP,
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(sequence "Q%u", 0, 31))>;
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// The ELF stub used for TLS-descriptor access saves every feasible
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// register. Only X0 and LR are clobbered.
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def CSR_AArch64_TLS_ELF
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: CalleeSavedRegs<(add (sequence "X%u", 1, 28), FP,
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(sequence "Q%u", 0, 31))>;
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def CSR_AArch64_AllRegs
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: CalleeSavedRegs<(add (sequence "W%u", 0, 30), WSP,
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(sequence "X%u", 0, 28), FP, LR, SP,
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(sequence "B%u", 0, 31), (sequence "H%u", 0, 31),
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(sequence "S%u", 0, 31), (sequence "D%u", 0, 31),
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(sequence "Q%u", 0, 31))>;
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