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5c9bb7119a
Moving these patterns from TableGen files to PerformDAGCombine() should allow us to generate better code by eliminating unnecessary shifts and extensions earlier. This also fixes a bug where the MAD pattern was calling SimplifyDemandedBits with a 24-bit mask on the first operand even when the full pattern wasn't being matched. This occasionally resulted in some instructions being incorrectly deleted from the program. v2: - Fix bug with 64-bit mul git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205731 91177308-0d34-0410-b5e6-96231b3b80d8
111 lines
2.6 KiB
C++
111 lines
2.6 KiB
C++
//=====-- AMDGPUSubtarget.h - Define Subtarget for the AMDIL ---*- C++ -*-====//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//==-----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief AMDGPU specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#ifndef AMDGPUSUBTARGET_H
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#define AMDGPUSUBTARGET_H
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#include "AMDGPU.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#define GET_SUBTARGETINFO_HEADER
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#include "AMDGPUGenSubtargetInfo.inc"
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#define MAX_CB_SIZE (1 << 16)
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namespace llvm {
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class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
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public:
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enum Generation {
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R600 = 0,
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R700,
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EVERGREEN,
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NORTHERN_ISLANDS,
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SOUTHERN_ISLANDS,
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SEA_ISLANDS
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};
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private:
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size_t DefaultSize[3];
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std::string DevName;
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bool Is64bit;
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bool Is32on64bit;
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bool DumpCode;
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bool R600ALUInst;
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bool HasVertexCache;
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short TexVTXClauseSize;
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enum Generation Gen;
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bool FP64;
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bool CaymanISA;
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bool EnableIRStructurizer;
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bool EnableIfCvt;
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unsigned WavefrontSize;
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bool CFALUBug;
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InstrItineraryData InstrItins;
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public:
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AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS);
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const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
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virtual void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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bool is64bit() const;
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bool hasVertexCache() const;
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short getTexVTXClauseSize() const;
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enum Generation getGeneration() const;
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bool hasHWFP64() const;
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bool hasCaymanISA() const;
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bool hasBFE() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasBFM() const {
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return hasBFE();
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}
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bool hasMulU24() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasMulI24() const {
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return (getGeneration() >= SOUTHERN_ISLANDS ||
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hasCaymanISA());
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}
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bool IsIRStructurizerEnabled() const;
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bool isIfCvtEnabled() const;
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unsigned getWavefrontSize() const;
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unsigned getStackEntrySize() const;
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bool hasCFAluBug() const;
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virtual bool enableMachineScheduler() const {
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return getGeneration() <= NORTHERN_ISLANDS;
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}
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// Helper functions to simplify if statements
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bool isTargetELF() const;
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std::string getDeviceName() const;
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virtual size_t getDefaultSize(uint32_t dim) const;
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bool dumpCode() const { return DumpCode; }
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bool r600ALUEncoding() const { return R600ALUInst; }
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};
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} // End namespace llvm
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#endif // AMDGPUSUBTARGET_H
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