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Summary: This allows specifying instructions that are available only in specific assembler variant. If AsmVariantName is specified then instruction will be presented only in MatchTable for this variant. If not specified then assembler variants will be determined based on AsmString. Also this allows splitting assembler match tables in same way as it is done in dissasembler. Reviewers: ab, tstellarAMD, craig.topper, vpykhtin Subscribers: wdng Differential Revision: https://reviews.llvm.org/D24249 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@280952 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
2003-08-03-PassCode.td | ||
2006-09-18-LargeInt.td | ||
2010-03-24-PrematureDefaults.td | ||
AnonDefinitionOnDemand.td | ||
AsmPredicateCondsEmission.td | ||
AsmVariant.td | ||
BitOffsetDecoder.td | ||
BitsInit.td | ||
BitsInitOverflow.td | ||
cast-list-initializer.td | ||
cast.td | ||
ClassInstanceValue.td | ||
CStyleComment.td | ||
Dag.td | ||
defmclass.td | ||
DefmInherit.td | ||
DefmInsideMultiClass.td | ||
eq.td | ||
eqbit.td | ||
FieldAccess.td | ||
foreach.td | ||
ForeachList.td | ||
ForeachLoop.td | ||
ForwardRef.td | ||
GeneralList.td | ||
if-empty-list-arg.td | ||
if.td | ||
ifbit.td | ||
Include.inc | ||
Include.td | ||
IntBitInit.td | ||
intrinsic-long-name.td | ||
intrinsic-varargs.td | ||
LazyChange.td | ||
LetInsideMultiClasses.td | ||
lisp.td | ||
list-element-bitref.td | ||
ListArgs.td | ||
ListArgsSimple.td | ||
listconcat.td | ||
ListConversion.td | ||
ListManip.td | ||
ListOfList.td | ||
ListSlices.td | ||
lit.local.cfg | ||
LoLoL.td | ||
math.td | ||
MultiClass.td | ||
MultiClassDefName.td | ||
MultiClassInherit.td | ||
MultiPat.td | ||
nested-comment.td | ||
NestedForeach.td | ||
Paste.td | ||
pr8330.td | ||
SetTheory.td | ||
SiblingForeach.td | ||
Slice.td | ||
strconcat.td | ||
String.td | ||
subst2.td | ||
subst.td | ||
SuperSubclassSameName.td | ||
TargetInstrInfo.td | ||
TargetInstrSpec.td | ||
TemplateArgRename.td | ||
Tree.td | ||
TreeNames.td | ||
trydecode-emission2.td | ||
trydecode-emission3.td | ||
trydecode-emission.td | ||
TwoLevelName.td | ||
UnsetBitInit.td | ||
UnterminatedComment.td | ||
usevalname.td | ||
ValidIdentifiers.td |