Pete Cooper 2d49689793 Added custom lowering for load->dec->store sequence in x86 when the EFLAGS registers is used ... by later instructions. Only done for DEC64m right now. Fixes <rdar://problem/6172640> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144705 91177308-0d34-0410-b5e6-96231b3b80d8		2011-11-15 21:57:53 +00:00
..
ARM	Add vmov.f32 to materialize f32 immediate splats which cannot be handled by	2011-11-15 02:12:34 +00:00
CBackend
CellSPU	Remove histogram tests.	2011-11-12 22:39:40 +00:00
CPP
Generic
MBlaze	Change the default scheduler from Latency to ILP, since Latency	2011-10-24 17:45:02 +00:00
Mips	Reapply r143206, with fixes. Disallow physical register lifetimes	2011-11-03 21:49:52 +00:00
MSP430	Remove the explicit request for "Latency" scheduling from MSP430,	2011-10-24 17:53:16 +00:00
PowerPC	test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll: [PR11218] Mark "REQUIRES: asserts" for now.	2011-10-28 23:11:03 +00:00
PTX	allow non-device function calls in PTX when natively handling device-side printf	2011-11-11 14:45:12 +00:00
SPARC
Thumb	Reapply r143206, with fixes. Disallow physical register lifetimes	2011-11-03 21:49:52 +00:00
Thumb2	Add vmov.f32 to materialize f32 immediate splats which cannot be handled by	2011-11-15 02:12:34 +00:00
X86	Added custom lowering for load->dec->store sequence in x86 when the EFLAGS registers is used	2011-11-15 21:57:53 +00:00
XCore	Don't fold negative offsets into cp / dp accesses to avoid relocation errors.	2011-11-01 11:31:53 +00:00