Simon Pilgrim e0a23dddf0 [X86][SSE] Replace 128-bit SSE41 PMOVSX intrinsics with native IR ...

This patches removes the x86.sse41.pmovsx* intrinsics, provides a suitable upgrade path and updates relevant tests to sign extend a subvector instead.

LLVM counterpart to D12835

Differential Revision: http://reviews.llvm.org/D13002

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248368 91177308-0d34-0410-b5e6-96231b3b80d8

2015-09-23 08:48:33 +00:00

..

AArch64

[AArch64] Emit clrex in the expanded cmpxchg fail block.

2015-09-22 17:21:44 +00:00

AMDGPU

LiveIntervalAnalysis: Avoid multiple connected liveness components

2015-09-22 22:37:44 +00:00

ARM

[ARM] Emit clrex in the expanded cmpxchg fail block.

2015-09-22 17:22:58 +00:00

BPF

[bpf] rename triple names bpf_be -> bpfeb

2015-06-05 16:11:14 +00:00

CPP

Fix CPP Backend for GEP API changes for opaque pointer types

2015-09-08 18:42:29 +00:00

Generic

Make the default triple optional by allowing an empty string

2015-09-16 05:34:32 +00:00

Hexagon

Update edge weights properly when merging blocks in if-conversion.

2015-09-18 20:22:41 +00:00

Inputs

DI: Require subprogram definitions to be distinct

2015-08-28 20:26:49 +00:00

Mips

[opaque pointer type] Add textual IR support for explicit type parameter for global aliases

2015-09-11 03:22:04 +00:00

MIR

Fix PR 24724 - The implicit register verifier shouldn't assume certain operand

2015-09-10 14:04:34 +00:00

MSP430

[opaque pointer type] Add textual IR support for explicit type parameter to gep operator

2015-03-13 18:20:45 +00:00

NVPTX

[NVPTX] Let NVPTX backend detect integer min and max patterns.

2015-08-26 23:22:02 +00:00

PowerPC

DAGCombiner: Replace store of FP constant after attemping store merges

2015-09-21 15:59:46 +00:00

SPARC

[SPARC] Switch to the Machine Scheduler.

2015-09-10 21:49:06 +00:00

SystemZ

[SystemZ] Fix expansion of ISD::FPOW and ISD::FSINCOS

2015-09-21 17:35:45 +00:00

Thumb

DI: Require subprogram definitions to be distinct

2015-08-28 20:26:49 +00:00

Thumb2

Scaling up values in ARMBaseInstrInfo::isProfitableToIfCvt() before they are scaled by a probability to avoid precision issue.

2015-09-18 18:19:40 +00:00

WebAssembly

[WebAssembly] Check in an initial CFG Stackifier pass

2015-09-16 16:51:30 +00:00

WinEH

[WinEH] Rip out the landingpad-based C++ EH state numbering code

2015-09-16 22:14:46 +00:00

X86

[X86][SSE] Replace 128-bit SSE41 PMOVSX intrinsics with native IR

2015-09-23 08:48:33 +00:00

XCore

[opaque pointer type] Add textual IR support for explicit type parameter for global aliases

2015-09-11 03:22:04 +00:00