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e28484a720
Work towards the unification of MIR and debug output by refactoring the interfaces. Add support for operand subreg index as an immediate to debug printing and use ::print in the MIRPrinter. Differential Review: https://reviews.llvm.org/D40965 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320209 91177308-0d34-0410-b5e6-96231b3b80d8
123 lines
4.0 KiB
C++
123 lines
4.0 KiB
C++
//===- MachineOperandTest.cpp ---------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/ADT/ilist_node.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/IR/ModuleSlotTracker.h"
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#include "llvm/Support/raw_ostream.h"
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#include "gtest/gtest.h"
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using namespace llvm;
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namespace {
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TEST(MachineOperandTest, ChangeToTargetIndexTest) {
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// Creating a MachineOperand to change it to TargetIndex
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MachineOperand MO = MachineOperand::CreateImm(50);
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// Checking some precondition on the newly created
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// MachineOperand.
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ASSERT_TRUE(MO.isImm());
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ASSERT_TRUE(MO.getImm() == 50);
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ASSERT_FALSE(MO.isTargetIndex());
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// Changing to TargetIndex with some arbitrary values
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// for index, offset and flags.
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MO.ChangeToTargetIndex(74, 57, 12);
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// Checking that the mutation to TargetIndex happened
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// correctly.
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ASSERT_TRUE(MO.isTargetIndex());
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ASSERT_TRUE(MO.getIndex() == 74);
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ASSERT_TRUE(MO.getOffset() == 57);
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ASSERT_TRUE(MO.getTargetFlags() == 12);
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}
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TEST(MachineOperandTest, PrintRegisterMask) {
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uint32_t Dummy;
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MachineOperand MO = MachineOperand::CreateRegMask(&Dummy);
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// Checking some preconditions on the newly created
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// MachineOperand.
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ASSERT_TRUE(MO.isRegMask());
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ASSERT_TRUE(MO.getRegMask() == &Dummy);
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// Print a MachineOperand containing a RegMask. Here we check that without a
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// TRI and IntrinsicInfo we still print a less detailed regmask.
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std::string str;
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raw_string_ostream OS(str);
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MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr);
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ASSERT_TRUE(OS.str() == "<regmask ...>");
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}
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TEST(MachineOperandTest, PrintSubReg) {
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// Create a MachineOperand with RegNum=1 and SubReg=5.
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MachineOperand MO = MachineOperand::CreateReg(
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/*Reg=*/1, /*isDef=*/false, /*isImp=*/false, /*isKill=*/false,
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/*isDead=*/false, /*isUndef=*/false, /*isEarlyClobber=*/false,
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/*SubReg=*/5, /*isDebug=*/false, /*isInternalRead=*/false);
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// Checking some preconditions on the newly created
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// MachineOperand.
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ASSERT_TRUE(MO.isReg());
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ASSERT_TRUE(MO.getReg() == 1);
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ASSERT_TRUE(MO.getSubReg() == 5);
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// Print a MachineOperand containing a SubReg. Here we check that without a
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// TRI and IntrinsicInfo we can still print the subreg index.
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std::string str;
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raw_string_ostream OS(str);
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MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr);
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ASSERT_TRUE(OS.str() == "%physreg1.subreg5");
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}
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TEST(MachineOperandTest, PrintCImm) {
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LLVMContext Context;
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APInt Int(128, UINT64_MAX);
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++Int;
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ConstantInt *CImm = ConstantInt::get(Context, Int);
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// Create a MachineOperand with an Imm=(UINT64_MAX + 1)
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MachineOperand MO = MachineOperand::CreateCImm(CImm);
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// Checking some preconditions on the newly created
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// MachineOperand.
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ASSERT_TRUE(MO.isCImm());
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ASSERT_TRUE(MO.getCImm() == CImm);
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ASSERT_TRUE(MO.getCImm()->getValue() == Int);
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// Print a MachineOperand containing a SubReg. Here we check that without a
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// TRI and IntrinsicInfo we can still print the subreg index.
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std::string str;
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raw_string_ostream OS(str);
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MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr);
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ASSERT_TRUE(OS.str() == "i128 18446744073709551616");
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}
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TEST(MachineOperandTest, PrintSubRegIndex) {
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// Create a MachineOperand with an immediate and print it as a subreg index.
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MachineOperand MO = MachineOperand::CreateImm(3);
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// Checking some preconditions on the newly created
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// MachineOperand.
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ASSERT_TRUE(MO.isImm());
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ASSERT_TRUE(MO.getImm() == 3);
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// Print a MachineOperand containing a SubRegIdx. Here we check that without a
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// TRI and IntrinsicInfo we can print the operand as a subreg index.
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std::string str;
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raw_string_ostream OS(str);
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ModuleSlotTracker DummyMST(nullptr);
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MachineOperand::printSubregIdx(OS, MO.getImm(), nullptr);
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ASSERT_TRUE(OS.str() == "%subreg.3");
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}
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} // end namespace
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