llvm/test/CodeGen/X86/2011-10-30-padd.ll
Nadav Rotem fb0dfbbff7 Fix pr11266.
On x86: (shl V, 1) -> add V,V

Hardware support for vector-shift is sparse and in many cases we scalarize the
result. Additionally, on sandybridge padd is faster than shl.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143311 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-30 13:24:22 +00:00

21 lines
450 B
LLVM

; RUN: llc < %s -march=x86 -mcpu=corei7 | FileCheck %s
;CHECK: addXX_test
;CHECK: padd
;CHECK: ret
define <16 x i8> @addXX_test(<16 x i8> %a) {
%b = add <16 x i8> %a, %a
ret <16 x i8> %b
}
;CHECK: instcombine_test
;CHECK: padd
;CHECK: ret
define <16 x i8> @instcombine_test(<16 x i8> %a) {
%b = shl <16 x i8> %a, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
ret <16 x i8> %b
}