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4e1fb18940
Allow the strategy to select SchedDFS. Allow the results of SchedDFS to affect initialization of the scheduler state. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173425 91177308-0d34-0410-b5e6-96231b3b80d8
196 lines
7.7 KiB
LLVM
196 lines
7.7 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mcpu=core2 -pre-RA-sched=source -enable-misched \
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; RUN: -misched-topdown -verify-machineinstrs \
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; RUN: | FileCheck %s -check-prefix=TOPDOWN
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; RUN: llc < %s -march=x86-64 -mcpu=core2 -pre-RA-sched=source -enable-misched \
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; RUN: -misched=ilpmin -verify-machineinstrs \
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; RUN: | FileCheck %s -check-prefix=ILPMIN
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; RUN: llc < %s -march=x86-64 -mcpu=core2 -pre-RA-sched=source -enable-misched \
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; RUN: -misched=ilpmax -verify-machineinstrs \
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; RUN: | FileCheck %s -check-prefix=ILPMAX
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;
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; Verify that the MI scheduler minimizes register pressure for a
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; uniform set of bottom-up subtrees (unrolled matrix multiply).
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;
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; For current top-down heuristics, ensure that some folded imulls have
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; been reordered with the stores. This tests the scheduler's cheap
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; alias analysis ability (that doesn't require any AliasAnalysis pass).
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;
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; TOPDOWN: %for.body
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; TOPDOWN: movl %{{.*}}, (
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; TOPDOWN: imull {{[0-9]*}}(
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; TOPDOWN: movl %{{.*}}, 4(
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; TOPDOWN: imull {{[0-9]*}}(
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; TOPDOWN: movl %{{.*}}, 8(
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; TOPDOWN: movl %{{.*}}, 12(
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; TOPDOWN: %for.end
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;
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; For -misched=ilpmin, verify that each expression subtree is
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; scheduled independently, and that the imull/adds are interleaved.
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;
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; ILPMIN: %for.body
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; ILPMIN: movl %{{.*}}, (
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; ILPMIN: imull
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; ILPMIN: imull
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; ILPMIN: addl
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; ILPMIN: imull
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; ILPMIN: addl
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; ILPMIN: imull
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; ILPMIN: addl
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; ILPMIN: movl %{{.*}}, 4(
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; ILPMIN: imull
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; ILPMIN: imull
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; ILPMIN: addl
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; ILPMIN: imull
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; ILPMIN: addl
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; ILPMIN: imull
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; ILPMIN: addl
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; ILPMIN: movl %{{.*}}, 8(
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; ILPMIN: imull
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; ILPMIN: imull
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; ILPMIN: addl
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; ILPMIN: imull
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; ILPMIN: addl
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; ILPMIN: imull
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; ILPMIN: addl
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; ILPMIN: movl %{{.*}}, 12(
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; ILPMIN: %for.end
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;
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; For -misched=ilpmax, verify that each expression subtree is
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; scheduled independently, and that the imull/adds are clustered.
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;
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; ILPMAX: %for.body
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; ILPMAX: movl %{{.*}}, (
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; ILPMAX: imull
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; ILPMAX: imull
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; ILPMAX: imull
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; ILPMAX: imull
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; ILPMAX: addl
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; ILPMAX: addl
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; ILPMAX: addl
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; ILPMAX: movl %{{.*}}, 4(
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; ILPMAX: imull
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; ILPMAX: imull
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; ILPMAX: imull
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; ILPMAX: imull
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; ILPMAX: addl
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; ILPMAX: addl
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; ILPMAX: addl
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; ILPMAX: movl %{{.*}}, 8(
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; ILPMAX: imull
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; ILPMAX: imull
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; ILPMAX: imull
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; ILPMAX: imull
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; ILPMAX: addl
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; ILPMAX: addl
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; ILPMAX: addl
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; ILPMAX: movl %{{.*}}, 12(
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; ILPMAX: %for.end
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define void @mmult([4 x i32]* noalias nocapture %m1, [4 x i32]* noalias nocapture %m2,
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[4 x i32]* noalias nocapture %m3) nounwind uwtable ssp {
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entry:
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
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%arrayidx8 = getelementptr inbounds [4 x i32]* %m1, i64 %indvars.iv, i64 0
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%tmp = load i32* %arrayidx8, align 4, !tbaa !0
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%arrayidx12 = getelementptr inbounds [4 x i32]* %m2, i64 0, i64 0
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%tmp1 = load i32* %arrayidx12, align 4, !tbaa !0
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%arrayidx8.1 = getelementptr inbounds [4 x i32]* %m1, i64 %indvars.iv, i64 1
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%tmp2 = load i32* %arrayidx8.1, align 4, !tbaa !0
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%arrayidx12.1 = getelementptr inbounds [4 x i32]* %m2, i64 1, i64 0
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%tmp3 = load i32* %arrayidx12.1, align 4, !tbaa !0
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%arrayidx8.2 = getelementptr inbounds [4 x i32]* %m1, i64 %indvars.iv, i64 2
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%tmp4 = load i32* %arrayidx8.2, align 4, !tbaa !0
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%arrayidx12.2 = getelementptr inbounds [4 x i32]* %m2, i64 2, i64 0
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%tmp5 = load i32* %arrayidx12.2, align 4, !tbaa !0
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%arrayidx8.3 = getelementptr inbounds [4 x i32]* %m1, i64 %indvars.iv, i64 3
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%tmp6 = load i32* %arrayidx8.3, align 4, !tbaa !0
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%arrayidx12.3 = getelementptr inbounds [4 x i32]* %m2, i64 3, i64 0
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%tmp8 = load i32* %arrayidx8, align 4, !tbaa !0
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%arrayidx12.137 = getelementptr inbounds [4 x i32]* %m2, i64 0, i64 1
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%tmp9 = load i32* %arrayidx12.137, align 4, !tbaa !0
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%tmp10 = load i32* %arrayidx8.1, align 4, !tbaa !0
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%arrayidx12.1.1 = getelementptr inbounds [4 x i32]* %m2, i64 1, i64 1
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%tmp11 = load i32* %arrayidx12.1.1, align 4, !tbaa !0
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%tmp12 = load i32* %arrayidx8.2, align 4, !tbaa !0
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%arrayidx12.2.1 = getelementptr inbounds [4 x i32]* %m2, i64 2, i64 1
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%tmp13 = load i32* %arrayidx12.2.1, align 4, !tbaa !0
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%tmp14 = load i32* %arrayidx8.3, align 4, !tbaa !0
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%arrayidx12.3.1 = getelementptr inbounds [4 x i32]* %m2, i64 3, i64 1
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%tmp15 = load i32* %arrayidx12.3.1, align 4, !tbaa !0
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%tmp16 = load i32* %arrayidx8, align 4, !tbaa !0
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%arrayidx12.239 = getelementptr inbounds [4 x i32]* %m2, i64 0, i64 2
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%tmp17 = load i32* %arrayidx12.239, align 4, !tbaa !0
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%tmp18 = load i32* %arrayidx8.1, align 4, !tbaa !0
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%arrayidx12.1.2 = getelementptr inbounds [4 x i32]* %m2, i64 1, i64 2
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%tmp19 = load i32* %arrayidx12.1.2, align 4, !tbaa !0
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%tmp20 = load i32* %arrayidx8.2, align 4, !tbaa !0
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%arrayidx12.2.2 = getelementptr inbounds [4 x i32]* %m2, i64 2, i64 2
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%tmp21 = load i32* %arrayidx12.2.2, align 4, !tbaa !0
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%tmp22 = load i32* %arrayidx8.3, align 4, !tbaa !0
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%arrayidx12.3.2 = getelementptr inbounds [4 x i32]* %m2, i64 3, i64 2
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%tmp23 = load i32* %arrayidx12.3.2, align 4, !tbaa !0
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%tmp24 = load i32* %arrayidx8, align 4, !tbaa !0
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%arrayidx12.341 = getelementptr inbounds [4 x i32]* %m2, i64 0, i64 3
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%tmp25 = load i32* %arrayidx12.341, align 4, !tbaa !0
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%tmp26 = load i32* %arrayidx8.1, align 4, !tbaa !0
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%arrayidx12.1.3 = getelementptr inbounds [4 x i32]* %m2, i64 1, i64 3
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%tmp27 = load i32* %arrayidx12.1.3, align 4, !tbaa !0
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%tmp28 = load i32* %arrayidx8.2, align 4, !tbaa !0
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%arrayidx12.2.3 = getelementptr inbounds [4 x i32]* %m2, i64 2, i64 3
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%tmp29 = load i32* %arrayidx12.2.3, align 4, !tbaa !0
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%tmp30 = load i32* %arrayidx8.3, align 4, !tbaa !0
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%arrayidx12.3.3 = getelementptr inbounds [4 x i32]* %m2, i64 3, i64 3
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%tmp31 = load i32* %arrayidx12.3.3, align 4, !tbaa !0
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%tmp7 = load i32* %arrayidx12.3, align 4, !tbaa !0
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%mul = mul nsw i32 %tmp1, %tmp
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%mul.1 = mul nsw i32 %tmp3, %tmp2
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%mul.2 = mul nsw i32 %tmp5, %tmp4
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%mul.3 = mul nsw i32 %tmp7, %tmp6
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%mul.138 = mul nsw i32 %tmp9, %tmp8
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%mul.1.1 = mul nsw i32 %tmp11, %tmp10
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%mul.2.1 = mul nsw i32 %tmp13, %tmp12
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%mul.3.1 = mul nsw i32 %tmp15, %tmp14
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%mul.240 = mul nsw i32 %tmp17, %tmp16
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%mul.1.2 = mul nsw i32 %tmp19, %tmp18
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%mul.2.2 = mul nsw i32 %tmp21, %tmp20
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%mul.3.2 = mul nsw i32 %tmp23, %tmp22
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%mul.342 = mul nsw i32 %tmp25, %tmp24
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%mul.1.3 = mul nsw i32 %tmp27, %tmp26
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%mul.2.3 = mul nsw i32 %tmp29, %tmp28
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%mul.3.3 = mul nsw i32 %tmp31, %tmp30
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%add.1 = add nsw i32 %mul.1, %mul
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%add.2 = add nsw i32 %mul.2, %add.1
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%add.3 = add nsw i32 %mul.3, %add.2
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%add.1.1 = add nsw i32 %mul.1.1, %mul.138
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%add.2.1 = add nsw i32 %mul.2.1, %add.1.1
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%add.3.1 = add nsw i32 %mul.3.1, %add.2.1
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%add.1.2 = add nsw i32 %mul.1.2, %mul.240
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%add.2.2 = add nsw i32 %mul.2.2, %add.1.2
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%add.3.2 = add nsw i32 %mul.3.2, %add.2.2
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%add.1.3 = add nsw i32 %mul.1.3, %mul.342
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%add.2.3 = add nsw i32 %mul.2.3, %add.1.3
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%add.3.3 = add nsw i32 %mul.3.3, %add.2.3
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%arrayidx16 = getelementptr inbounds [4 x i32]* %m3, i64 %indvars.iv, i64 0
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store i32 %add.3, i32* %arrayidx16, align 4, !tbaa !0
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%arrayidx16.1 = getelementptr inbounds [4 x i32]* %m3, i64 %indvars.iv, i64 1
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store i32 %add.3.1, i32* %arrayidx16.1, align 4, !tbaa !0
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%arrayidx16.2 = getelementptr inbounds [4 x i32]* %m3, i64 %indvars.iv, i64 2
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store i32 %add.3.2, i32* %arrayidx16.2, align 4, !tbaa !0
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%arrayidx16.3 = getelementptr inbounds [4 x i32]* %m3, i64 %indvars.iv, i64 3
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store i32 %add.3.3, i32* %arrayidx16.3, align 4, !tbaa !0
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%indvars.iv.next = add i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, 4
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body
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ret void
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}
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!0 = metadata !{metadata !"int", metadata !1}
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!1 = metadata !{metadata !"omnipotent char", metadata !2}
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!2 = metadata !{metadata !"Simple C/C++ TBAA"}
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