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e3e43d9d57
I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304787 91177308-0d34-0410-b5e6-96231b3b80d8
241 lines
8.2 KiB
C++
241 lines
8.2 KiB
C++
//===-- llvm/CodeGen/GlobalISel/Legalizer.cpp -----------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file implements the LegalizerHelper class to legalize individual
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/// instructions and the LegalizePass wrapper pass for the primary
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/// legalization.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/Legalizer.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <iterator>
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#define DEBUG_TYPE "legalizer"
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using namespace llvm;
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char Legalizer::ID = 0;
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INITIALIZE_PASS_BEGIN(Legalizer, DEBUG_TYPE,
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"Legalize the Machine IR a function's Machine IR", false,
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false)
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INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
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INITIALIZE_PASS_END(Legalizer, DEBUG_TYPE,
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"Legalize the Machine IR a function's Machine IR", false,
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false)
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Legalizer::Legalizer() : MachineFunctionPass(ID) {
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initializeLegalizerPass(*PassRegistry::getPassRegistry());
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}
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void Legalizer::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<TargetPassConfig>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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void Legalizer::init(MachineFunction &MF) {
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}
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bool Legalizer::combineExtracts(MachineInstr &MI, MachineRegisterInfo &MRI,
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const TargetInstrInfo &TII) {
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bool Changed = false;
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if (MI.getOpcode() != TargetOpcode::G_EXTRACT)
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return Changed;
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unsigned NumDefs = (MI.getNumOperands() - 1) / 2;
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unsigned SrcReg = MI.getOperand(NumDefs).getReg();
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MachineInstr &SeqI = *MRI.def_instr_begin(SrcReg);
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if (SeqI.getOpcode() != TargetOpcode::G_SEQUENCE)
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return Changed;
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unsigned NumSeqSrcs = (SeqI.getNumOperands() - 1) / 2;
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bool AllDefsReplaced = true;
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// Try to match each register extracted with a corresponding insertion formed
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// by the G_SEQUENCE.
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for (unsigned Idx = 0, SeqIdx = 0; Idx < NumDefs; ++Idx) {
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MachineOperand &ExtractMO = MI.getOperand(Idx);
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assert(ExtractMO.isReg() && ExtractMO.isDef() &&
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"unexpected extract operand");
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unsigned ExtractReg = ExtractMO.getReg();
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unsigned ExtractPos = MI.getOperand(NumDefs + Idx + 1).getImm();
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while (SeqIdx < NumSeqSrcs &&
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SeqI.getOperand(2 * SeqIdx + 2).getImm() < ExtractPos)
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++SeqIdx;
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if (SeqIdx == NumSeqSrcs) {
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AllDefsReplaced = false;
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continue;
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}
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unsigned OrigReg = SeqI.getOperand(2 * SeqIdx + 1).getReg();
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if (SeqI.getOperand(2 * SeqIdx + 2).getImm() != ExtractPos ||
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MRI.getType(OrigReg) != MRI.getType(ExtractReg)) {
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AllDefsReplaced = false;
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continue;
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}
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assert(!TargetRegisterInfo::isPhysicalRegister(OrigReg) &&
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"unexpected physical register in G_SEQUENCE");
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// Finally we can replace the uses.
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MRI.replaceRegWith(ExtractReg, OrigReg);
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}
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if (AllDefsReplaced) {
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// If SeqI was the next instruction in the BB and we removed it, we'd break
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// the outer iteration.
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assert(std::next(MachineBasicBlock::iterator(MI)) != SeqI &&
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"G_SEQUENCE does not dominate G_EXTRACT");
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MI.eraseFromParent();
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if (MRI.use_empty(SrcReg))
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SeqI.eraseFromParent();
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Changed = true;
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}
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return Changed;
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}
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bool Legalizer::combineMerges(MachineInstr &MI, MachineRegisterInfo &MRI,
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const TargetInstrInfo &TII) {
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if (MI.getOpcode() != TargetOpcode::G_UNMERGE_VALUES)
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return false;
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unsigned NumDefs = MI.getNumOperands() - 1;
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unsigned SrcReg = MI.getOperand(NumDefs).getReg();
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MachineInstr &MergeI = *MRI.def_instr_begin(SrcReg);
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if (MergeI.getOpcode() != TargetOpcode::G_MERGE_VALUES)
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return false;
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if (MergeI.getNumOperands() - 1 != NumDefs)
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return false;
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// FIXME: is a COPY appropriate if the types mismatch? We know both registers
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// are allocatable by now.
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if (MRI.getType(MI.getOperand(0).getReg()) !=
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MRI.getType(MergeI.getOperand(1).getReg()))
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return false;
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for (unsigned Idx = 0; Idx < NumDefs; ++Idx)
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MRI.replaceRegWith(MI.getOperand(Idx).getReg(),
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MergeI.getOperand(Idx + 1).getReg());
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MI.eraseFromParent();
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if (MRI.use_empty(MergeI.getOperand(0).getReg()))
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MergeI.eraseFromParent();
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return true;
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}
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bool Legalizer::runOnMachineFunction(MachineFunction &MF) {
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// If the ISel pipeline failed, do not bother running that pass.
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if (MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::FailedISel))
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return false;
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DEBUG(dbgs() << "Legalize Machine IR for: " << MF.getName() << '\n');
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init(MF);
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const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
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MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);
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LegalizerHelper Helper(MF);
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// FIXME: an instruction may need more than one pass before it is legal. For
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// example on most architectures <3 x i3> is doubly-illegal. It would
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// typically proceed along a path like: <3 x i3> -> <3 x i8> -> <8 x i8>. We
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// probably want a worklist of instructions rather than naive iterate until
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// convergence for performance reasons.
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bool Changed = false;
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MachineBasicBlock::iterator NextMI;
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for (auto &MBB : MF) {
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for (auto MI = MBB.begin(); MI != MBB.end(); MI = NextMI) {
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// Get the next Instruction before we try to legalize, because there's a
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// good chance MI will be deleted.
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NextMI = std::next(MI);
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// Only legalize pre-isel generic instructions: others don't have types
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// and are assumed to be legal.
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if (!isPreISelGenericOpcode(MI->getOpcode()))
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continue;
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unsigned NumNewInsns = 0;
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SmallVector<MachineInstr *, 4> WorkList;
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Helper.MIRBuilder.recordInsertions([&](MachineInstr *MI) {
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// Only legalize pre-isel generic instructions.
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// Legalization process could generate Target specific pseudo
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// instructions with generic types. Don't record them
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if (isPreISelGenericOpcode(MI->getOpcode())) {
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++NumNewInsns;
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WorkList.push_back(MI);
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}
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});
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WorkList.push_back(&*MI);
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bool Changed = false;
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LegalizerHelper::LegalizeResult Res;
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unsigned Idx = 0;
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do {
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Res = Helper.legalizeInstrStep(*WorkList[Idx]);
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// Error out if we couldn't legalize this instruction. We may want to
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// fall back to DAG ISel instead in the future.
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if (Res == LegalizerHelper::UnableToLegalize) {
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Helper.MIRBuilder.stopRecordingInsertions();
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if (Res == LegalizerHelper::UnableToLegalize) {
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reportGISelFailure(MF, TPC, MORE, "gisel-legalize",
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"unable to legalize instruction",
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*WorkList[Idx]);
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return false;
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}
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}
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Changed |= Res == LegalizerHelper::Legalized;
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++Idx;
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#ifndef NDEBUG
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if (NumNewInsns) {
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DEBUG(dbgs() << ".. .. Emitted " << NumNewInsns << " insns\n");
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for (auto I = WorkList.end() - NumNewInsns, E = WorkList.end();
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I != E; ++I)
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DEBUG(dbgs() << ".. .. New MI: "; (*I)->print(dbgs()));
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NumNewInsns = 0;
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}
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#endif
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} while (Idx < WorkList.size());
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Helper.MIRBuilder.stopRecordingInsertions();
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}
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}
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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for (auto &MBB : MF) {
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for (auto MI = MBB.begin(); MI != MBB.end(); MI = NextMI) {
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// Get the next Instruction before we try to legalize, because there's a
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// good chance MI will be deleted.
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NextMI = std::next(MI);
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// combineExtracts erases MI.
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if (combineExtracts(*MI, MRI, TII)) {
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Changed = true;
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continue;
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}
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Changed |= combineMerges(*MI, MRI, TII);
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}
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}
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return Changed;
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}
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