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5443e7d790
Now that 3.3 is branched, we are re-enabling virtual registers to help iron out bugs before the next release. Some of the post-RA passes do not play well with virtual registers, so we disable them for now. The needed functionality of the PrologEpilogInserter pass is copied to a new backend-specific NVPTXPrologEpilog pass. The test for this commit is not breaking the existing tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182998 91177308-0d34-0410-b5e6-96231b3b80d8
27 lines
676 B
LLVM
27 lines
676 B
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
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define ptx_device float @test_fabsf(float %f) {
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; CHECK: abs.f32 %f{{[0-9]+}}, %f{{[0-9]+}};
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; CHECK: ret;
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%x = call float @llvm.fabs.f32(float %f)
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ret float %x
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}
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define ptx_device double @test_fabs(double %d) {
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; CHECK: abs.f64 %fl{{[0-9]+}}, %fl{{[0-9]+}};
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; CHECK: ret;
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%x = call double @llvm.fabs.f64(double %d)
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ret double %x
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}
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define float @test_nvvm_sqrt(float %a) {
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%val = call float @llvm.nvvm.sqrt.f(float %a)
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ret float %val
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}
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declare float @llvm.fabs.f32(float)
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declare double @llvm.fabs.f64(double)
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declare float @llvm.nvvm.sqrt.f(float)
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