llvm/CodeGen at e610c324e1a56843abdff27a1bf30d188255a23b - llvm

RPCS3/llvm

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History

Chandler Carruth e610c324e1 [x86] Teach the new vector shuffle lowering to use BLENDPS and BLENDPD.

These are super simple. They even take precedence over crazy
instructions like INSERTPS because they have very high throughput on
modern x86 chips.

I still have to teach the integer shuffle variants about this to avoid
so many domain crossings. However, due to the particular instructions
available, that's a touch more complex and so a separate patch.

Also, the backend doesn't seem to realize it can commute blend
instructions by negating the mask. That would help remove a number of
copies here. Suggestions on how to do this welcome, it's an area I'm
less familiar with.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217744 91177308-0d34-0410-b5e6-96231b3b80d8

2014-09-14 23:43:33 +00:00

AArch64

[FastISel][AArch64] Add support for non-native types for logical ops.

2014-09-13 23:46:28 +00:00

ARM

[ARM] Add Thumb-2 code size optimization regression test for LSR (register).

2014-09-11 10:45:50 +00:00

CPP

…

Generic

Add a regression test to sanity check the PBQP allocator.

2014-09-03 18:04:10 +00:00