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e61b6779e4
This was completely broken if there was ever a struct argument, as this information is thrown away during the argument analysis. The offsets as passed in to LowerFormalArguments are not useful, as they partially depend on the legalized result register type, and they don't consider the alignment in the first place. Ignore the Ins array, and instead figure out from the raw IR type what we need to do. This seems to fix the padding computation if the DAG lowering is forced (and stops breaking arguments following padded arguments if the arguments were only partially lowered in the IR) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337021 91177308-0d34-0410-b5e6-96231b3b80d8
66 lines
2.3 KiB
C++
66 lines
2.3 KiB
C++
//===-- AMDGPUMachineFunctionInfo.cpp ---------------------------------------=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUMachineFunction.h"
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#include "AMDGPUSubtarget.h"
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#include "AMDGPUPerfHintAnalysis.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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using namespace llvm;
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AMDGPUMachineFunction::AMDGPUMachineFunction(const MachineFunction &MF) :
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MachineFunctionInfo(),
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LocalMemoryObjects(),
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ExplicitKernArgSize(0),
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MaxKernArgAlign(0),
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LDSSize(0),
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IsEntryFunction(AMDGPU::isEntryFunctionCC(MF.getFunction().getCallingConv())),
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NoSignedZerosFPMath(MF.getTarget().Options.NoSignedZerosFPMath),
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MemoryBound(false),
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WaveLimiter(false) {
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const AMDGPUSubtarget &ST = AMDGPUSubtarget::get(MF);
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// FIXME: Should initialize KernArgSize based on ExplicitKernelArgOffset,
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// except reserved size is not correctly aligned.
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const Function &F = MF.getFunction();
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if (auto *Resolver = MF.getMMI().getResolver()) {
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if (AMDGPUPerfHintAnalysis *PHA = static_cast<AMDGPUPerfHintAnalysis*>(
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Resolver->getAnalysisIfAvailable(&AMDGPUPerfHintAnalysisID, true))) {
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MemoryBound = PHA->isMemoryBound(&F);
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WaveLimiter = PHA->needsWaveLimiter(&F);
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}
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}
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CallingConv::ID CC = F.getCallingConv();
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if (CC == CallingConv::AMDGPU_KERNEL || CC == CallingConv::SPIR_KERNEL)
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ExplicitKernArgSize = ST.getExplicitKernArgSize(F, MaxKernArgAlign);
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}
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unsigned AMDGPUMachineFunction::allocateLDSGlobal(const DataLayout &DL,
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const GlobalValue &GV) {
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auto Entry = LocalMemoryObjects.insert(std::make_pair(&GV, 0));
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if (!Entry.second)
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return Entry.first->second;
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unsigned Align = GV.getAlignment();
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if (Align == 0)
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Align = DL.getABITypeAlignment(GV.getValueType());
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/// TODO: We should sort these to minimize wasted space due to alignment
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/// padding. Currently the padding is decided by the first encountered use
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/// during lowering.
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unsigned Offset = LDSSize = alignTo(LDSSize, Align);
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Entry.first->second = Offset;
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LDSSize += DL.getTypeAllocSize(GV.getValueType());
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return Offset;
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}
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