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86050dc8cc
- This fixed a number of bugs in if-converter, tail merging, and post-allocation scheduler. If-converter now runs branch folding / tail merging first to maximize if-conversion opportunities. - Also changed the t2IT instruction slightly. It now defines the ITSTATE register which is read by instructions in the IT block. - Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't change the instruction ordering in the IT block (since IT mask has been finalized). It also ensures no other instructions can be scheduled between instructions in the IT block. This is not yet enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
34 lines
969 B
LLVM
34 lines
969 B
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s
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; rdar://7354379
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declare double @floor(double) nounwind readnone
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define void @t(i1 %a, double %b) {
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entry:
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br i1 %a, label %bb3, label %bb1
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bb1: ; preds = %entry
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unreachable
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bb3: ; preds = %entry
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br i1 %a, label %bb7, label %bb5
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bb5: ; preds = %bb3
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unreachable
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bb7: ; preds = %bb3
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br i1 %a, label %bb11, label %bb9
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bb9: ; preds = %bb7
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; CHECK: cmp r0, #0
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; CHECK: cmp r0, #0
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; CHECK-NEXT: cbnz
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%0 = tail call double @floor(double %b) nounwind readnone ; <double> [#uses=0]
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br label %bb11
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bb11: ; preds = %bb9, %bb7
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%1 = getelementptr i32* undef, i32 0
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store i32 0, i32* %1
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ret void
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}
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