llvm/test/DebugInfo/MIR
Wolfgang Pieb 5c49cf1beb Reapply r294532, reverted in r294787.
Store instructions can have more than one memory operand as a result
of optimizations that fold different stores into one.
When we identify spill instructions to generate DBG_VALUE instructions
to record the spilling of a variable, we disregard stores with 
multiple memory operands for now. We may miss some relevant spills but
the handling is a bit more complex, so we'll do it in a different patch.

This fixes PR31935.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295093 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-14 19:08:45 +00:00
..
ARM Fix LLVM's use of DW_OP_bit_piece in DWARF expressions. 2016-12-09 20:43:40 +00:00
X86 Reapply r294532, reverted in r294787. 2017-02-14 19:08:45 +00:00
lit.local.cfg