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b85e4eba85
for pre-2.9 bitcode files. We keep x86 unaligned loads, movnt, crc32, and the target indep prefetch change. As usual, updating the testsuite is a PITA. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133337 91177308-0d34-0410-b5e6-96231b3b80d8
75 lines
3.0 KiB
LLVM
75 lines
3.0 KiB
LLVM
; RUN: opt < %s -basicaa -dse -S
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
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target triple = "i386-apple-darwin10.0"
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@g80 = external global i8 ; <i8*> [#uses=3]
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declare signext i8 @foo(i8 signext, i8 signext) nounwind readnone ssp
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declare i32 @func68(i32) nounwind readonly ssp
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; PR4815
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define void @test1(i32 %int32p54) noreturn nounwind ssp {
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entry:
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br label %bb
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bb: ; preds = %bb, %entry
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%storemerge = phi i8 [ %2, %bb ], [ 1, %entry ] ; <i8> [#uses=1]
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store i8 %storemerge, i8* @g80
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%0 = tail call i32 @func68(i32 1) nounwind ssp ; <i32> [#uses=1]
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%1 = trunc i32 %0 to i8 ; <i8> [#uses=1]
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store i8 %1, i8* @g80, align 1
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store i8 undef, i8* @g80, align 1
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%2 = tail call signext i8 @foo(i8 signext undef, i8 signext 1) nounwind ; <i8> [#uses=1]
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br label %bb
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}
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define fastcc i32 @test2() nounwind ssp {
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bb14: ; preds = %bb4
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%0 = bitcast i8* undef to i8** ; <i8**> [#uses=1]
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%1 = getelementptr inbounds i8** %0, i64 undef ; <i8**> [#uses=1]
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%2 = bitcast i8** %1 to i16* ; <i16*> [#uses=2]
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%3 = getelementptr inbounds i16* %2, i64 undef ; <i16*> [#uses=1]
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%4 = bitcast i16* %3 to i8* ; <i8*> [#uses=1]
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%5 = getelementptr inbounds i8* %4, i64 undef ; <i8*> [#uses=1]
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%6 = getelementptr inbounds i16* %2, i64 undef ; <i16*> [#uses=1]
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store i16 undef, i16* %6, align 2
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%7 = getelementptr inbounds i8* %5, i64 undef ; <i8*> [#uses=1]
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* %7, i8* undef, i64 undef, i32 1, i1 false)
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unreachable
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}
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
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; rdar://7635088
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define i32 @test3() {
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entry:
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ret i32 0
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dead:
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%P2 = getelementptr i32 *%P2, i32 52
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%Q2 = getelementptr i32 *%Q2, i32 52
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store i32 4, i32* %P2
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store i32 4, i32* %Q2
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br label %dead
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}
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; PR3141
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%struct.ada__tags__dispatch_table = type { [1 x i32] }
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%struct.f393a00_1__object = type { %struct.ada__tags__dispatch_table*, i8 }
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%struct.f393a00_2__windmill = type { %struct.f393a00_1__object, i16 }
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define void @test4(%struct.f393a00_2__windmill* %a, %struct.f393a00_2__windmill* %b) {
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entry:
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%t = alloca %struct.f393a00_2__windmill ; <%struct.f393a00_2__windmill*> [#uses=1]
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%0 = getelementptr %struct.f393a00_2__windmill* %t, i32 0, i32 0, i32 0 ; <%struct.ada__tags__dispatch_table**> [#uses=1]
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%1 = load %struct.ada__tags__dispatch_table** null, align 4 ; <%struct.ada__tags__dispatch_table*> [#uses=1]
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%2 = load %struct.ada__tags__dispatch_table** %0, align 8 ; <%struct.ada__tags__dispatch_table*> [#uses=1]
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store %struct.ada__tags__dispatch_table* %2, %struct.ada__tags__dispatch_table** null, align 4
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store %struct.ada__tags__dispatch_table* %1, %struct.ada__tags__dispatch_table** null, align 4
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ret void
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}
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