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llvm/lib/Target/Alpha
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Evan Cheng 23329f5e03 SelectNodeTo() may return a SDOperand that is different from the input. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29726 91177308-0d34-0410-b5e6-96231b3b80d8
2006-08-16 07:30:09 +00:00
..
.cvsignore ignore generated files 2005-09-07 23:47:44 +00:00
Alpha.h - Refactor the code that resolve basic block references to a TargetJITInfo 2006-07-25 20:40:54 +00:00
Alpha.td getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. 2006-05-18 00:12:58 +00:00
AlphaAsmPrinter.cpp 0 offsets for memory operands 2006-07-03 17:57:34 +00:00
AlphaCodeEmitter.cpp Resolve BB references with relocation. 2006-07-27 18:21:10 +00:00
AlphaInstrFormats.td Let the alpha breakage begin. First Formals and RET. next Calls 2006-06-12 18:09:24 +00:00
AlphaInstrInfo.cpp these are copies too 2006-03-09 18:18:51 +00:00
AlphaInstrInfo.h isStoreToStackSlot 2006-02-03 03:07:37 +00:00
AlphaInstrInfo.td CALLSEQ_* produces chain even if that's not needed. 2006-08-11 09:03:33 +00:00
AlphaISelDAGToDAG.cpp SelectNodeTo() may return a SDOperand that is different from the input. 2006-08-16 07:30:09 +00:00
AlphaISelLowering.cpp Eliminate use of getNode that takes a vector. 2006-08-11 17:38:39 +00:00
AlphaISelLowering.h inline asm, at least for floats 2006-06-21 13:37:27 +00:00
AlphaJITInfo.cpp Resolve BB references with relocation. 2006-07-27 18:21:10 +00:00
AlphaJITInfo.h Resolve BB references with relocation. 2006-07-27 18:21:10 +00:00
AlphaRegisterInfo.cpp Let the alpha breakage begin. First Formals and RET. next Calls 2006-06-12 18:09:24 +00:00
AlphaRegisterInfo.h getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. 2006-05-18 00:12:58 +00:00
AlphaRegisterInfo.td Add dwarf register numbering to register data. 2006-03-24 21:15:58 +00:00
AlphaRelocations.h Patches to make the LLVM sources more -pedantic clean. Patch provided 2006-05-24 17:04:05 +00:00
AlphaSchedule.td Alpha Scheduling classes 2006-03-09 17:16:45 +00:00
AlphaSubtarget.cpp Give full control of subtarget features over to table generated code. 2005-10-26 17:30:34 +00:00
AlphaSubtarget.h Alpha Scheduling classes 2006-03-09 17:16:45 +00:00
AlphaTargetMachine.cpp - Refactor the code that resolve basic block references to a TargetJITInfo 2006-07-25 20:40:54 +00:00
AlphaTargetMachine.h Refactor a bunch of includes so that TargetMachine.h doesn't have to include 2006-05-12 06:33:49 +00:00
Makefile Autogen subtarget information from .td files. 2005-10-23 22:15:34 +00:00
README.txt ignore ordered/unordered for now 2006-06-04 00:25:51 +00:00

README.txt 

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
Fix Ordered/Unordered FP stuff


%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
improve bytezap opertunities
ulong %foo(ulong %y) {
entry:
        %tmp = and ulong %y,  65535
        %tmp2 = shr ulong %tmp,  ubyte 3
        ret ulong %tmp2
}


compiles to a 3 instruction sequence without instcombine
        zapnot $16,3,$0
        srl $0,3,$0
        ret $31,($26),1
 
After instcombine you get
ulong %foo(ulong %y) {
entry:
        %tmp = shr ulong %y, ubyte 3            ; <ulong> [#uses=1]
        %tmp2 = and ulong %tmp, 8191            ; <ulong> [#uses=1]
        ret ulong %tmp2
}

which compiles to
        lda $0,8191($31)
        srl $16,3,$1
        and $1,$0,$0
        ret $31,($26),1