Tom Stellard ec4cb3346d R600/SI: Use a ComplexPattern for DS loads and stores ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216278 91177308-0d34-0410-b5e6-96231b3b80d8

2014-08-22 18:49:33 +00:00

..

AArch64

[FastISel][AArch64] Add support for variable shift.

2014-08-21 23:06:07 +00:00

ARM

[ARM] Move the implementation of the target hooks related to copy-related

2014-08-22 18:05:22 +00:00

CPP

IR: add "cmpxchg weak" variant to support permitted failure.

2014-06-13 14:24:07 +00:00

Generic

Use "weak alias" instead of "alias weak"

2014-07-30 22:51:54 +00:00

Hexagon

DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range.

2014-08-06 00:21:25 +00:00

Inputs

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Mips

[mips] Don't use odd-numbered float registers for double arguments for fastcc

2014-08-22 09:23:22 +00:00

MSP430

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NVPTX

[NVPTX] Add some extra tests for mul.wide to test non-power-of-two source types

2014-07-23 20:23:49 +00:00

PowerPC

Reapply [FastISel] Let the target decide first if it wants to materialize a constant (215588).

2014-08-19 19:05:24 +00:00

R600

R600/SI: Use a ComplexPattern for DS loads and stores

2014-08-22 18:49:33 +00:00

SPARC

IR: add "cmpxchg weak" variant to support permitted failure.

2014-06-13 14:24:07 +00:00

SystemZ

IR: add "cmpxchg weak" variant to support permitted failure.

2014-06-13 14:24:07 +00:00

Thumb

Thumb1 load/store optimizer: Improve code to materialize new base register.

2014-08-21 17:11:03 +00:00

Thumb2

[ARM] Enable DP copy, load and store instructions for FPv4-SP

2014-08-21 12:50:31 +00:00

X86

DAGCombiner: Make concat_vector combine safe for EVTs and concat_vectors with many arguments.

2014-08-21 13:28:02 +00:00

XCore

llvm/test/CodeGen/XCore/dwarf_debug.ll: Fix not to be affected by *-win32.

2014-07-04 11:58:03 +00:00