Jun Bum Lim 5ffe2bacea Improve ISel using across lane min/max reduction ... In vectorized integer min/max reduction code, the final "reduce" step is sub-optimal. In AArch64, this change wll combine : %svn0 = vector_shuffle %0, undef<2,3,u,u> %smax0 = smax %0, svn0 %svn3 = vector_shuffle %smax0, undef<1,u,u,u> %sc = setcc %smax0, %svn3, gt %n0 = extract_vector_elt %sc, #0 %n1 = extract_vector_elt %smax0, #0 %n2 = extract_vector_elt $smax0, #1 %result = select %n0, %n1, n2 becomes : %1 = smaxv %0 %result = extract_vector_elt %1, 0 This change extends r246790. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247575 91177308-0d34-0410-b5e6-96231b3b80d8		2015-09-14 16:19:52 +00:00
..
AArch64	Improve ISel using across lane min/max reduction	2015-09-14 16:19:52 +00:00
AMDGPU	AMDGPU/SI: Fold operands through REG_SEQUENCE instructions	2015-09-09 15:43:26 +00:00
ARM	[ARM] Extract shifts out of multiply-by-constant	2015-09-14 15:19:41 +00:00
BPF
CPP
Generic	Use function attribute "stackrealign" to decide whether stack	2015-09-11 18:54:38 +00:00
Hexagon
Inputs
Mips	[opaque pointer type] Add textual IR support for explicit type parameter for global aliases	2015-09-11 03:22:04 +00:00
MIR	Fix PR 24724 - The implicit register verifier shouldn't assume certain operand	2015-09-10 14:04:34 +00:00
MSP430
NVPTX
PowerPC	[opaque pointer type] Add textual IR support for explicit type parameter for global aliases	2015-09-11 03:22:04 +00:00
SPARC	[SPARC] Switch to the Machine Scheduler.	2015-09-10 21:49:06 +00:00
SystemZ
Thumb
Thumb2
WebAssembly	[WebAssembly] Update target datalayout strings.	2015-09-09 20:54:31 +00:00
WinEH	[IR] Print the label operands of a catchpad like an invoke	2015-09-11 17:27:52 +00:00
X86	[X86][MMX] Added shuffle decodes for MMX/3DNow! shuffles.	2015-09-13 11:28:45 +00:00
XCore	[opaque pointer type] Add textual IR support for explicit type parameter for global aliases	2015-09-11 03:22:04 +00:00