Juergen Ributzka dd7a7107c1 [FastISel][AArch64] Add target-dependent instruction selection for Add/Sub.
There is already target-dependent instruction selection support for Adds/Subs to
support compares and the intrinsics with overflow check. This takes advantage of
the existing infrastructure to also support Add/Sub, which allows the folding of
immediates, sign-/zero-extends, and shifts.

This fixes rdar://problem/18207316.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217007 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-03 01:38:36 +00:00
..
2014-09-02 22:32:20 +00:00
2014-09-02 22:28:02 +00:00
2014-08-14 15:15:09 +00:00