Andrew V. Tischenko f047f45845 Added cost of ZEROALL and ZEROUPPER instrs in btver2 cpu. ...

Differential Revision https://reviews.llvm.org/D35834


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309269 91177308-0d34-0410-b5e6-96231b3b80d8

2017-07-27 13:12:08 +00:00

..

AArch64

[AArch64] Add a test for float argument passing to win64 vararg functions

2017-07-25 19:57:22 +00:00

AMDGPU

[AMDGPU] Optimize SI_IF lowering for simple if regions

2017-07-26 21:29:15 +00:00

ARM

[ARM] GlobalISel: Map G_GLOBAL_VALUE to GPR

2017-07-26 11:01:13 +00:00

AVR

[AVR] Remove the instrumentation pass

2017-07-23 23:39:11 +00:00

BPF

[DAG] Fix typo preventing some stores merges to truncated stores.

2017-07-23 02:06:28 +00:00

Generic

[AVR] Add/remove XFAILs to get the backend passing Generic CodeGen tests

2017-07-16 23:33:50 +00:00

Hexagon

[Hexagon] Recognize C4_cmpneqi, C4_cmpltei and C4_cmplteui in NewValueJump

2017-07-24 19:35:48 +00:00

Inputs

[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.

2016-04-15 15:57:41 +00:00

Lanai

CodeGen: Rename DEBUG_TYPE to match passnames

2017-05-25 21:26:32 +00:00

Mips

Fix endianness bug in DAGCombiner::visitTRUNCATE and visitEXTRACT_VECTOR_ELT

2017-07-25 09:40:35 +00:00

MIR

AMDGPU: Implement memory model

2017-07-21 21:19:23 +00:00

MSP430

[DAG] Improve Aliasing of operations to static alloca

2017-07-18 20:06:24 +00:00

Nios2

[Nios2] Target registration

2017-05-29 09:48:30 +00:00

NVPTX

[NVPTX] Add lowering of i128 params.

2017-07-20 21:16:03 +00:00

PowerPC

[PowerPC] enable optimizeCompareInstr for branch with static branch hint

2017-07-27 08:14:48 +00:00

SPARC

[SPARC] Clean up the support for disabling fsmuld and fmuls instructions.

2017-07-20 20:09:11 +00:00

SystemZ

[SystemZ] test update

2017-07-21 13:14:17 +00:00

Thumb

[ARM] Allow rematerialization of ARM Thumb literal pool loads

2017-07-14 08:23:56 +00:00

Thumb2

[ARM] Adjust ifcvt heuristic for the diamond ifcvt case

2017-07-12 13:23:10 +00:00

WebAssembly

Revert r308273 to reinstate part of r308100.

2017-07-19 04:15:30 +00:00

WinEH

Avoid infinite loops in branch folding

2016-12-12 23:05:38 +00:00

X86

Added cost of ZEROALL and ZEROUPPER instrs in btver2 cpu.

2017-07-27 13:12:08 +00:00

XCore

[DAG] Improve Aliasing of operations to static alloca

2017-07-18 20:06:24 +00:00