Tim Northover f52efce72d ARM: implement MRS/MSR (banked reg) system instructions. ...

These are system-only instructions for CPUs with virtualization
extensions, allowing a hypervisor easy access to all of the various
different AArch32 registers.

rdar://problem/17861345

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215700 91177308-0d34-0410-b5e6-96231b3b80d8

2014-08-15 10:47:12 +00:00

..

AArch64

Condition codes AL and NV are invalid in the aliases that use

2014-06-10 13:11:35 +00:00

ARM

ARM: implement MRS/MSR (banked reg) system instructions.

2014-08-15 10:47:12 +00:00

Mips

[mips][mips64r6] Correct cond names in the cmp.cond.[ds] instructions

2014-07-09 10:40:20 +00:00

PowerPC

Update disassembler test to check the full dccci/iccci form.

2014-08-09 14:01:10 +00:00

Sparc

Reduce verbiage of lit.local.cfg files

2014-06-09 22:42:55 +00:00

SystemZ

[SystemZ] Add MC support for LEDBRA, LEXBRA and LDXBRA

2014-07-10 11:00:55 +00:00

X86

[X86] AVX512: Add disassembler support for compressed displacement

2014-07-17 17:04:56 +00:00

XCore

Reduce verbiage of lit.local.cfg files

2014-06-09 22:42:55 +00:00