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46090914b7
mips16/mips32 floating point interoperability. This patch fixes returns from mips16 functions so that if the function was in fact called by a mips32 hard float routine, then values that would have been returned in floating point registers are so returned. Mips16 mode has no floating point instructions so there is no way to load values into floating point registers. This is needed when returning float, double, single complex, double complex in the Mips ABI. Helper functions in libc for mips16 are available to do this. For efficiency purposes, these helper functions have a different calling convention from normal Mips calls. Registers v0,v1,a0,a1 are used to pass parameters instead of a0,a1,a2,a3. This is because v0,v1,a0,a1 are the natural registers used to return floating point values in soft float. These values can then be moved to the appropriate floating point registers with no extra cost. The only register that is modified is ra in this call. The helper functions make sure that the return values are in the floating point registers that they would be in if soft float was not in effect (which it is for mips16, though the soft float is implemented using a mips32 library that uses hard float). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181641 91177308-0d34-0410-b5e6-96231b3b80d8
236 lines
9.5 KiB
TableGen
236 lines
9.5 KiB
TableGen
//===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This describes the calling conventions for Mips architecture.
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//===----------------------------------------------------------------------===//
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/// CCIfSubtarget - Match if the current subtarget has a feature F.
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class CCIfSubtarget<string F, CCAction A>:
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CCIf<!strconcat("State.getTarget().getSubtarget<MipsSubtarget>().", F), A>;
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//===----------------------------------------------------------------------===//
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// Mips O32 Calling Convention
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//===----------------------------------------------------------------------===//
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// Only the return rules are defined here for O32. The rules for argument
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// passing are defined in MipsISelLowering.cpp.
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def RetCC_MipsO32 : CallingConv<[
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// i32 are returned in registers V0, V1, A0, A1
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CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>,
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// f32 are returned in registers F0, F2
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CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
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// f64 are returned in register D0, D1
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CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0, D1]>>>
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]>;
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//===----------------------------------------------------------------------===//
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// Mips N32/64 Calling Convention
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//===----------------------------------------------------------------------===//
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def CC_MipsN : CallingConv<[
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// Promote i8/i16 arguments to i32.
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CCIfType<[i8, i16], CCPromoteToType<i32>>,
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// Integer arguments are passed in integer registers.
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CCIfType<[i32], CCAssignToRegWithShadow<[A0, A1, A2, A3,
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T0, T1, T2, T3],
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[F12, F13, F14, F15,
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F16, F17, F18, F19]>>,
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CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64,
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T0_64, T1_64, T2_64, T3_64],
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[D12_64, D13_64, D14_64, D15_64,
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D16_64, D17_64, D18_64, D19_64]>>,
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// f32 arguments are passed in single precision FP registers.
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CCIfType<[f32], CCAssignToRegWithShadow<[F12, F13, F14, F15,
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F16, F17, F18, F19],
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[A0_64, A1_64, A2_64, A3_64,
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T0_64, T1_64, T2_64, T3_64]>>,
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// f64 arguments are passed in double precision FP registers.
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CCIfType<[f64], CCAssignToRegWithShadow<[D12_64, D13_64, D14_64, D15_64,
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D16_64, D17_64, D18_64, D19_64],
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[A0_64, A1_64, A2_64, A3_64,
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T0_64, T1_64, T2_64, T3_64]>>,
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// All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
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CCIfType<[i32, f32], CCAssignToStack<4, 8>>,
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CCIfType<[i64, f64], CCAssignToStack<8, 8>>
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]>;
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// N32/64 variable arguments.
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// All arguments are passed in integer registers.
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def CC_MipsN_VarArg : CallingConv<[
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// Promote i8/i16 arguments to i32.
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CCIfType<[i8, i16], CCPromoteToType<i32>>,
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CCIfType<[i32, f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
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CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64,
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T0_64, T1_64, T2_64, T3_64]>>,
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// All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
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CCIfType<[i32, f32], CCAssignToStack<4, 8>>,
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CCIfType<[i64, f64], CCAssignToStack<8, 8>>
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]>;
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def RetCC_MipsN : CallingConv<[
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// i32 are returned in registers V0, V1
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CCIfType<[i32], CCAssignToReg<[V0, V1]>>,
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// i64 are returned in registers V0_64, V1_64
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CCIfType<[i64], CCAssignToReg<[V0_64, V1_64]>>,
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// f32 are returned in registers F0, F2
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CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
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// f64 are returned in registers D0, D2
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CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>>
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]>;
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// In soft-mode, register A0_64, instead of V1_64, is used to return a long
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// double value.
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def RetCC_F128Soft : CallingConv<[
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CCIfType<[i64], CCAssignToReg<[V0_64, A0_64]>>
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]>;
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//===----------------------------------------------------------------------===//
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// Mips EABI Calling Convention
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//===----------------------------------------------------------------------===//
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def CC_MipsEABI : CallingConv<[
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// Promote i8/i16 arguments to i32.
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CCIfType<[i8, i16], CCPromoteToType<i32>>,
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// Integer arguments are passed in integer registers.
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CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
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// Single fp arguments are passed in pairs within 32-bit mode
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CCIfType<[f32], CCIfSubtarget<"isSingleFloat()",
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CCAssignToReg<[F12, F13, F14, F15, F16, F17, F18, F19]>>>,
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CCIfType<[f32], CCIfSubtarget<"isNotSingleFloat()",
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CCAssignToReg<[F12, F14, F16, F18]>>>,
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// The first 4 double fp arguments are passed in single fp registers.
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CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()",
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CCAssignToReg<[D6, D7, D8, D9]>>>,
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// Integer values get stored in stack slots that are 4 bytes in
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// size and 4-byte aligned.
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CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
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// Integer values get stored in stack slots that are 8 bytes in
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// size and 8-byte aligned.
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CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToStack<8, 8>>>
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]>;
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def RetCC_MipsEABI : CallingConv<[
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// i32 are returned in registers V0, V1
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CCIfType<[i32], CCAssignToReg<[V0, V1]>>,
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// f32 are returned in registers F0, F1
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CCIfType<[f32], CCAssignToReg<[F0, F1]>>,
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// f64 are returned in register D0
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CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0]>>>
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]>;
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//===----------------------------------------------------------------------===//
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// Mips FastCC Calling Convention
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//===----------------------------------------------------------------------===//
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def CC_MipsO32_FastCC : CallingConv<[
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// f64 arguments are passed in double-precision floating pointer registers.
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CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7, D8, D9]>>,
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// Stack parameter slots for f64 are 64-bit doublewords and 8-byte aligned.
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CCIfType<[f64], CCAssignToStack<8, 8>>
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]>;
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def CC_MipsN_FastCC : CallingConv<[
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// Integer arguments are passed in integer registers.
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CCIfType<[i64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, T0_64, T1_64,
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T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
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T8_64, V1_64]>>,
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// f64 arguments are passed in double-precision floating pointer registers.
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CCIfType<[f64], CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, D4_64, D5_64,
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D6_64, D7_64, D8_64, D9_64, D10_64, D11_64,
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D12_64, D13_64, D14_64, D15_64, D16_64, D17_64,
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D18_64, D19_64]>>,
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// Stack parameter slots for i64 and f64 are 64-bit doublewords and
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// 8-byte aligned.
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CCIfType<[i64, f64], CCAssignToStack<8, 8>>
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]>;
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def CC_Mips_FastCC : CallingConv<[
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// Handles byval parameters.
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CCIfByVal<CCPassByVal<4, 4>>,
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// Promote i8/i16 arguments to i32.
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CCIfType<[i8, i16], CCPromoteToType<i32>>,
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// Integer arguments are passed in integer registers. All scratch registers,
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// except for AT, V0 and T9, are available to be used as argument registers.
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CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6,
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T7, T8, V1]>>,
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// f32 arguments are passed in single-precision floating pointer registers.
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CCIfType<[f32], CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10,
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F11, F12, F13, F14, F15, F16, F17, F18, F19]>>,
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// Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned.
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CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
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CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>,
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CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FastCC>>,
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CCDelegateTo<CC_MipsN_FastCC>
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]>;
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//==
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def CC_Mips16RetHelper : CallingConv<[
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// Integer arguments are passed in integer registers.
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CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>
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]>;
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//===----------------------------------------------------------------------===//
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// Mips Calling Convention Dispatch
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//===----------------------------------------------------------------------===//
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def RetCC_Mips : CallingConv<[
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CCIfSubtarget<"isABI_EABI()", CCDelegateTo<RetCC_MipsEABI>>,
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CCIfSubtarget<"isABI_N32()", CCDelegateTo<RetCC_MipsN>>,
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CCIfSubtarget<"isABI_N64()", CCDelegateTo<RetCC_MipsN>>,
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CCDelegateTo<RetCC_MipsO32>
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]>;
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//===----------------------------------------------------------------------===//
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// Callee-saved register lists.
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//===----------------------------------------------------------------------===//
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def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP,
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(sequence "S%u", 7, 0))>;
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def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
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(sequence "S%u", 7, 0))>;
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def CSR_N32 : CalleeSavedRegs<(add D31_64, D29_64, D27_64, D25_64, D24_64,
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D23_64, D22_64, D21_64, RA_64, FP_64, GP_64,
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(sequence "S%u_64", 7, 0))>;
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def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64,
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GP_64, (sequence "S%u_64", 7, 0))>;
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def CSR_Mips16RetHelper :
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CalleeSavedRegs<(add V0, V1, (sequence "A%u", 3, 0), S0, S1)>;
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